From: Matt Birkholz <matt@birkholz.chandler.az.us>
Date: Thu, 8 Mar 2012 03:33:33 +0000 (-0700)
Subject: svm: Added 32bit offsets to explicit-coding-type "address".
X-Git-Tag: release-9.2.0~274
X-Git-Url: https://birchwood-abbey.net/git?a=commitdiff_plain;h=3bd478500a05ee33bb4a35747539193c1a70f9ee;p=mit-scheme.git

svm: Added 32bit offsets to explicit-coding-type "address".

Compilation of win32/wf_user.bin produces block offsets like #x11168
and #x10a38.
---

diff --git a/src/compiler/machines/svm/assembler-rules.scm b/src/compiler/machines/svm/assembler-rules.scm
index c12a16fd1..8d0f0e970 100644
--- a/src/compiler/machines/svm/assembler-rules.scm
+++ b/src/compiler/machines/svm/assembler-rules.scm
@@ -121,6 +121,13 @@ USA.
     offset
     oscale)
 
+  (define-code-sequence (offset (_ base word-register)
+				(_ offset signed-32)
+				(_ oscale scale-factor))
+    base
+    offset
+    oscale)
+
   (define-code-sequence (indexed (_ base word-register)
 				 (_ offset unsigned-8)
 				 (_ oscale scale-factor)
diff --git a/src/microcode/svm1-defns.h b/src/microcode/svm1-defns.h
index 6267b73da..be2193623 100644
--- a/src/microcode/svm1-defns.h
+++ b/src/microcode/svm1-defns.h
@@ -2,7 +2,7 @@
 
 DO NOT EDIT: this file was generated by a program.
 
-Copyright (C) 2011 Massachusetts Institute of Technology
+Copyright (C) 2012 Massachusetts Institute of Technology
 
 This is free software; see the source for copying conditions. There is NO
 warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
@@ -21,7 +21,7 @@ warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 #define SVM1_REG_DYNAMIC_LINK 4
 
 #define SVM1_ADDR_START_CODE 0x01
-#define SVM1_ADDR_END_CODE 0x20
+#define SVM1_ADDR_END_CODE 0x23
 
 #define SVM1_ADDR_BINDINGS(binder) \
   binder (SVM1_ADDR_INDIR, indir); \
@@ -31,6 +31,9 @@ warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   binder (SVM1_ADDR_OFFSET_S16_B, offset_s16_b); \
   binder (SVM1_ADDR_OFFSET_S16_W, offset_s16_w); \
   binder (SVM1_ADDR_OFFSET_S16_F, offset_s16_f); \
+  binder (SVM1_ADDR_OFFSET_S32_B, offset_s32_b); \
+  binder (SVM1_ADDR_OFFSET_S32_W, offset_s32_w); \
+  binder (SVM1_ADDR_OFFSET_S32_F, offset_s32_f); \
   binder (SVM1_ADDR_INDEX_B_B, index_b_b); \
   binder (SVM1_ADDR_INDEX_B_W, index_b_w); \
   binder (SVM1_ADDR_INDEX_B_F, index_b_f); \
@@ -90,117 +93,132 @@ warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   DECODE_WORD_REGISTER (base); \
   DECODE_SIGNED_16 (offset)
 
-#define SVM1_ADDR_INDEX_B_B 0x08
+#define SVM1_ADDR_OFFSET_S32_B 0x08
+#define DECODE_SVM1_ADDR_OFFSET_S32_B(base, offset) \
+  DECODE_WORD_REGISTER (base); \
+  DECODE_SIGNED_32 (offset)
+
+#define SVM1_ADDR_OFFSET_S32_W 0x09
+#define DECODE_SVM1_ADDR_OFFSET_S32_W(base, offset) \
+  DECODE_WORD_REGISTER (base); \
+  DECODE_SIGNED_32 (offset)
+
+#define SVM1_ADDR_OFFSET_S32_F 0x0a
+#define DECODE_SVM1_ADDR_OFFSET_S32_F(base, offset) \
+  DECODE_WORD_REGISTER (base); \
+  DECODE_SIGNED_32 (offset)
+
+#define SVM1_ADDR_INDEX_B_B 0x0b
 #define DECODE_SVM1_ADDR_INDEX_B_B(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_B_W 0x09
+#define SVM1_ADDR_INDEX_B_W 0x0c
 #define DECODE_SVM1_ADDR_INDEX_B_W(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_B_F 0x0a
+#define SVM1_ADDR_INDEX_B_F 0x0d
 #define DECODE_SVM1_ADDR_INDEX_B_F(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_W_B 0x0b
+#define SVM1_ADDR_INDEX_W_B 0x0e
 #define DECODE_SVM1_ADDR_INDEX_W_B(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_W_W 0x0c
+#define SVM1_ADDR_INDEX_W_W 0x0f
 #define DECODE_SVM1_ADDR_INDEX_W_W(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_W_F 0x0d
+#define SVM1_ADDR_INDEX_W_F 0x10
 #define DECODE_SVM1_ADDR_INDEX_W_F(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_F_B 0x0e
+#define SVM1_ADDR_INDEX_F_B 0x11
 #define DECODE_SVM1_ADDR_INDEX_F_B(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_F_W 0x0f
+#define SVM1_ADDR_INDEX_F_W 0x12
 #define DECODE_SVM1_ADDR_INDEX_F_W(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_INDEX_F_F 0x10
+#define SVM1_ADDR_INDEX_F_F 0x13
 #define DECODE_SVM1_ADDR_INDEX_F_F(base, offset, index) \
   DECODE_WORD_REGISTER (base); \
   DECODE_UNSIGNED_8 (offset); \
   DECODE_WORD_REGISTER (index)
 
-#define SVM1_ADDR_PREDEC_B 0x11
+#define SVM1_ADDR_PREDEC_B 0x14
 #define DECODE_SVM1_ADDR_PREDEC_B(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_PREDEC_W 0x12
+#define SVM1_ADDR_PREDEC_W 0x15
 #define DECODE_SVM1_ADDR_PREDEC_W(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_PREDEC_F 0x13
+#define SVM1_ADDR_PREDEC_F 0x16
 #define DECODE_SVM1_ADDR_PREDEC_F(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_PREINC_B 0x14
+#define SVM1_ADDR_PREINC_B 0x17
 #define DECODE_SVM1_ADDR_PREINC_B(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_PREINC_W 0x15
+#define SVM1_ADDR_PREINC_W 0x18
 #define DECODE_SVM1_ADDR_PREINC_W(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_PREINC_F 0x16
+#define SVM1_ADDR_PREINC_F 0x19
 #define DECODE_SVM1_ADDR_PREINC_F(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_POSTDEC_B 0x17
+#define SVM1_ADDR_POSTDEC_B 0x1a
 #define DECODE_SVM1_ADDR_POSTDEC_B(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_POSTDEC_W 0x18
+#define SVM1_ADDR_POSTDEC_W 0x1b
 #define DECODE_SVM1_ADDR_POSTDEC_W(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_POSTDEC_F 0x19
+#define SVM1_ADDR_POSTDEC_F 0x1c
 #define DECODE_SVM1_ADDR_POSTDEC_F(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_POSTINC_B 0x1a
+#define SVM1_ADDR_POSTINC_B 0x1d
 #define DECODE_SVM1_ADDR_POSTINC_B(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_POSTINC_W 0x1b
+#define SVM1_ADDR_POSTINC_W 0x1e
 #define DECODE_SVM1_ADDR_POSTINC_W(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_POSTINC_F 0x1c
+#define SVM1_ADDR_POSTINC_F 0x1f
 #define DECODE_SVM1_ADDR_POSTINC_F(base) \
   DECODE_WORD_REGISTER (base)
 
-#define SVM1_ADDR_PCR_S8 0x1d
+#define SVM1_ADDR_PCR_S8 0x20
 #define DECODE_SVM1_ADDR_PCR_S8(value) \
   DECODE_SIGNED_8 (value)
 
-#define SVM1_ADDR_PCR_S16 0x1e
+#define SVM1_ADDR_PCR_S16 0x21
 #define DECODE_SVM1_ADDR_PCR_S16(value) \
   DECODE_SIGNED_16 (value)
 
-#define SVM1_ADDR_PCR_S32 0x1f
+#define SVM1_ADDR_PCR_S32 0x22
 #define DECODE_SVM1_ADDR_PCR_S32(value) \
   DECODE_SIGNED_32 (value)
 
diff --git a/src/microcode/svm1-interp.c b/src/microcode/svm1-interp.c
index 72c59f073..4df83ea41 100644
--- a/src/microcode/svm1-interp.c
+++ b/src/microcode/svm1-interp.c
@@ -1307,6 +1307,24 @@ DEFINE_ADDRESS_DECODER (offset_s16_f)
   MAKE_OFFSET_ADDRESS (base, offset, SFLOAT);
 }
 
+DEFINE_ADDRESS_DECODER (offset_s32_b)
+{
+  DECODE_SVM1_ADDR_OFFSET_S32_B (base, offset);
+  MAKE_OFFSET_ADDRESS (base, offset, SBYTE);
+}
+
+DEFINE_ADDRESS_DECODER (offset_s32_w)
+{
+  DECODE_SVM1_ADDR_OFFSET_S32_W (base, offset);
+  MAKE_OFFSET_ADDRESS (base, offset, SWORD);
+}
+
+DEFINE_ADDRESS_DECODER (offset_s32_f)
+{
+  DECODE_SVM1_ADDR_OFFSET_S32_F (base, offset);
+  MAKE_OFFSET_ADDRESS (base, offset, SFLOAT);
+}
+
 static word_t
 indexed_address_value (address_t * address)
 {