From 79cdea461a6a0d12f050f77f712e98f0fc738ede Mon Sep 17 00:00:00 2001 From: Taylor R Campbell Date: Sun, 13 Jan 2019 22:52:06 +0000 Subject: [PATCH] Fill in some more files, add some build goo, fix some bugs. Invent a way to do assembler macros so we can do legible branch tensioning rules and reuse ADRP/ADD patterns. --- src/compiler/choose-machine.sh | 6 + src/compiler/configure | 4 +- src/compiler/machines/aarch64/TODO | 3 - src/compiler/machines/aarch64/assmd.scm | 78 ++ .../aarch64/{order-be.scm => big-endian.scm} | 0 src/compiler/machines/aarch64/coerce.scm | 57 + src/compiler/machines/aarch64/compiler.pkg | 4 +- src/compiler/machines/aarch64/compiler.sf | 2 + src/compiler/machines/aarch64/decls.scm | 3 +- src/compiler/machines/aarch64/endian.scm | 1 + src/compiler/machines/aarch64/insmac.scm | 116 ++ .../aarch64/{instr.scm => instr1.scm} | 1147 +++-------------- src/compiler/machines/aarch64/instr2.scm | 754 +++++++++++ src/compiler/machines/aarch64/instrf.scm | 32 + src/compiler/machines/aarch64/insutl.scm | 272 ++++ src/compiler/machines/aarch64/lapgen.scm | 354 ++++- .../{order-le.scm => little-endian.scm} | 0 src/compiler/machines/aarch64/machine.scm | 6 +- src/compiler/machines/aarch64/rules1.scm | 4 +- src/compiler/machines/aarch64/rules2.scm | 2 +- src/compiler/machines/aarch64/rules3.scm | 43 +- src/compiler/machines/aarch64/rulfix.scm | 5 +- src/compiler/machines/aarch64/rulflo.scm | 32 + src/microcode/aclocal.m4 | 3 + src/microcode/cmpauxmd/aarch64.m4 | 29 + src/microcode/cmpintmd/aarch64-config.h | 33 + src/microcode/cmpintmd/aarch64.c | 44 +- src/microcode/confshared.h | 4 +- 28 files changed, 2006 insertions(+), 1032 deletions(-) create mode 100644 src/compiler/machines/aarch64/assmd.scm rename src/compiler/machines/aarch64/{order-be.scm => big-endian.scm} (100%) create mode 100644 src/compiler/machines/aarch64/coerce.scm create mode 120000 src/compiler/machines/aarch64/endian.scm create mode 100644 src/compiler/machines/aarch64/insmac.scm rename src/compiler/machines/aarch64/{instr.scm => instr1.scm} (52%) create mode 100644 src/compiler/machines/aarch64/instr2.scm create mode 100644 src/compiler/machines/aarch64/instrf.scm create mode 100644 src/compiler/machines/aarch64/insutl.scm rename src/compiler/machines/aarch64/{order-le.scm => little-endian.scm} (100%) create mode 100644 src/compiler/machines/aarch64/rulflo.scm create mode 100644 src/microcode/cmpauxmd/aarch64.m4 create mode 100644 src/microcode/cmpintmd/aarch64-config.h diff --git a/src/compiler/choose-machine.sh b/src/compiler/choose-machine.sh index 48947f6d8..61bf6f3c4 100755 --- a/src/compiler/choose-machine.sh +++ b/src/compiler/choose-machine.sh @@ -43,6 +43,12 @@ svm1-32be|svm1-32le|svm1-64be|svm1-64le) exit 0 esac +case ${TARGET_ARCH} in +aarch64be|aarch64le) + echo aarch64 + exit 0 +esac + if test -d "${HERE}/machines/${TARGET_ARCH}"; then echo "${TARGET_ARCH}" exit 0 diff --git a/src/compiler/configure b/src/compiler/configure index bf04e0cd8..640274e38 100755 --- a/src/compiler/configure +++ b/src/compiler/configure @@ -67,10 +67,10 @@ svm1-64be|svm1-64le) esac case ${TARGET_ARCH} in -svm1-32be|svm1-64be) +svm1-32be|svm1-64be|aarch64be) ln -sf big-endian.scm machine/endian.scm ;; -svm1-32le|svm1-64le) +svm1-32le|svm1-64le|aarch64le) ln -sf little-endian.scm machine/endian.scm ;; esac diff --git a/src/compiler/machines/aarch64/TODO b/src/compiler/machines/aarch64/TODO index 08af65f71..4553b6e04 100644 --- a/src/compiler/machines/aarch64/TODO +++ b/src/compiler/machines/aarch64/TODO @@ -1,8 +1,5 @@ - Make it work. - [ ] assmd [ ] cmpauxmd - [ ] coerce - [ ] insmac [ ] instr: branch tensioning, review it all, simd, float [ ] insutl [ ] logical immediate encoding diff --git a/src/compiler/machines/aarch64/assmd.scm b/src/compiler/machines/aarch64/assmd.scm new file mode 100644 index 000000000..aedb36042 --- /dev/null +++ b/src/compiler/machines/aarch64/assmd.scm @@ -0,0 +1,78 @@ +#| -*-Scheme-*- + +Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, + 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, + 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, + 2017, 2018, 2019 Massachusetts Institute of Technology + +This file is part of MIT/GNU Scheme. + +MIT/GNU Scheme is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or (at +your option) any later version. + +MIT/GNU Scheme is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with MIT/GNU Scheme; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, +USA. + +|# + +;;;; Assembler Machine Dependencies. AArch64 version + +(declare (usual-integrations)) + +(define-integrable maximum-padding-length + ;; Instruction length is always a multiple of 32 bits + 32) + +(define-integrable padding-string + ;; Pad with HLT #0 instructions + (unsigned-integer->bit-string 32 #xd4400000)) + +(define-integrable block-offset-width + ;; Block offsets are always 16 bit words + 16) + +(define-integrable maximum-block-offset + ;; PC always aligned on 32-bit boundary + (- (expt 2 (1+ block-offset-width)) 4)) + +(define-integrable (block-offset->bit-string offset start?) + (unsigned-integer->bit-string block-offset-width + (+ (* 2 offset) + (if start? 0 1)))) + +;;; Machine dependent instruction order + +(define (instruction-initial-position block) + (case endianness + ((BIG) (bit-string-length block)) + ((LITTLE) 0) + (else (error "Unknown endianness:" endianness)))) + +(define (instruction-insert! bits block position receiver) + (let ((l (bit-string-length bits))) + (case endianness + ((BIG) + (let ((new-position (- position l))) + (bit-substring-move-right! bits 0 l block new-position) + (receiver new-position))) + ((LITTLE) + (let ((new-position (+ position l))) + (bit-substring-move-right! bits 0 l block position) + (receiver new-position))) + (else + (error "Unknown endianness:" endianness))))) + +(define (instruction-append x y) + (case endianness + ((BIG) (bit-string-append-reversed x y)) + ((LITTLE) (bit-string-append x y)) + (else (error "Unknown endianness:" endianness)))) diff --git a/src/compiler/machines/aarch64/order-be.scm b/src/compiler/machines/aarch64/big-endian.scm similarity index 100% rename from src/compiler/machines/aarch64/order-be.scm rename to src/compiler/machines/aarch64/big-endian.scm diff --git a/src/compiler/machines/aarch64/coerce.scm b/src/compiler/machines/aarch64/coerce.scm new file mode 100644 index 000000000..399641f53 --- /dev/null +++ b/src/compiler/machines/aarch64/coerce.scm @@ -0,0 +1,57 @@ +#| -*-Scheme-*- + +Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, + 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, + 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, + 2017, 2018, 2019 Massachusetts Institute of Technology + +This file is part of MIT/GNU Scheme. + +MIT/GNU Scheme is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or (at +your option) any later version. + +MIT/GNU Scheme is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with MIT/GNU Scheme; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, +USA. + +|# + +;;;; AArch64 Specific Coercions + +(declare (usual-integrations)) + +(define make-coercion + (coercion-maker + `((UNSIGNED . ,coerce-unsigned-integer) + (SIGNED . ,coerce-signed-integer)))) + +(define coerce-1-bit-unsigned (make-coercion 'UNSIGNED 1)) +(define coerce-2-bit-unsigned (make-coercion 'UNSIGNED 2)) +(define coerce-3-bit-unsigned (make-coercion 'UNSIGNED 3)) +(define coerce-4-bit-unsigned (make-coercion 'UNSIGNED 4)) +(define coerce-5-bit-unsigned (make-coercion 'UNSIGNED 5)) +(define coerce-6-bit-unsigned (make-coercion 'UNSIGNED 6)) +(define coerce-7-bit-unsigned (make-coercion 'UNSIGNED 7)) +(define coerce-8-bit-unsigned (make-coercion 'UNSIGNED 8)) + +(define coerce-12-bit-unsigned (make-coercion 'UNSIGNED 12)) +(define coerce-14-bit-unsigned (make-coercion 'UNSIGNED 14)) +(define coerce-16-bit-unsigned (make-coercion 'UNSIGNED 16)) +(define coerce-32-bit-unsigned (make-coercion 'UNSIGNED 32)) +(define coerce-64-bit-unsigned (make-coercion 'UNSIGNED 64)) + +(define coerce-7-bit-signed (make-coercion 'SIGNED 7)) +(define coerce-9-bit-signed (make-coercion 'SIGNED 9)) + +(define coerce-19-bit-signed (make-coercion 'SIGNED 19)) +(define coerce-26-bit-signed (make-coercion 'SIGNED 26)) +(define coerce-32-bit-signed (make-coercion 'SIGNED 32)) +(define coerce-64-bit-signed (make-coercion 'SIGNED 64)) diff --git a/src/compiler/machines/aarch64/compiler.pkg b/src/compiler/machines/aarch64/compiler.pkg index 52a7ad963..c5bffcdc2 100644 --- a/src/compiler/machines/aarch64/compiler.pkg +++ b/src/compiler/machines/aarch64/compiler.pkg @@ -36,6 +36,8 @@ USA. "base/sets" ;set abstraction "base/mvalue" ;multiple-value support "base/scode" ;SCode abstraction + "rtlbase/valclass" ;RTL: value classes + "machines/aarch64/endian" ;byte order "machines/aarch64/machine" ;machine dependent stuff "back/asutl" ;back-end odds and ends "base/utils" ;odds and ends @@ -63,7 +65,6 @@ USA. "rtlbase/rtlcfg" ;RTL: CFG types "rtlbase/rtlobj" ;RTL: CFG objects "rtlbase/regset" ;RTL: register sets - "rtlbase/valclass" ;RTL: value classes "back/insseq" ;LAP instruction sequences ) @@ -766,6 +767,7 @@ USA. (export (compiler top-level) assemble)) +#; (define-package (compiler disassembler) (files "machines/aarch64/dassm1" "machines/aarch64/dassm2" diff --git a/src/compiler/machines/aarch64/compiler.sf b/src/compiler/machines/aarch64/compiler.sf index 74b77c285..f5bf8f0f9 100644 --- a/src/compiler/machines/aarch64/compiler.sf +++ b/src/compiler/machines/aarch64/compiler.sf @@ -67,6 +67,8 @@ USA. ((access initialize-package! environment))) (sf-and-load '("base/pmlook") '(compiler pattern-matcher/lookup)) (sf-and-load '("base/pmpars") '(compiler pattern-matcher/parser)) + (sf-and-load '("rtlbase/valclass") '(compiler)) + (sf-and-load '("machines/aarch64/endian") '(compiler)) (sf-and-load '("machines/aarch64/machine") '(compiler)) (fluid-let ((sf/default-declarations '((integrate-external "insseq") diff --git a/src/compiler/machines/aarch64/decls.scm b/src/compiler/machines/aarch64/decls.scm index 66ace9402..d92feb2a7 100644 --- a/src/compiler/machines/aarch64/decls.scm +++ b/src/compiler/machines/aarch64/decls.scm @@ -343,7 +343,8 @@ USA. "lapgn1" "lapgn2" "lapgn3" "linear" "regmap" "symtab" "syntax") (filename/append "machines/aarch64" - "dassm1" "insmac" "lapopt" "machine" "rgspcm" + #;"dassm1" + "insmac" "lapopt" "machine" "rgspcm" "rulrew") (filename/append "fggen" "declar" "fggen" "canon") diff --git a/src/compiler/machines/aarch64/endian.scm b/src/compiler/machines/aarch64/endian.scm new file mode 120000 index 000000000..df05313d1 --- /dev/null +++ b/src/compiler/machines/aarch64/endian.scm @@ -0,0 +1 @@ +little-endian.scm \ No newline at end of file diff --git a/src/compiler/machines/aarch64/insmac.scm b/src/compiler/machines/aarch64/insmac.scm new file mode 100644 index 000000000..3c3de986f --- /dev/null +++ b/src/compiler/machines/aarch64/insmac.scm @@ -0,0 +1,116 @@ +#| -*-Scheme-*- + +Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, + 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, + 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, + 2017, 2018, 2019 Massachusetts Institute of Technology + +This file is part of MIT/GNU Scheme. + +MIT/GNU Scheme is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or (at +your option) any later version. + +MIT/GNU Scheme is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with MIT/GNU Scheme; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, +USA. + +|# + +;;;; AArch64 Instruction Set Macros + +(declare (usual-integrations)) + +(define (parse-instruction form forms early? environment) + (assert (not early?)) + (receive (expansion bits) (process* form forms environment) + bits + expansion)) + +(define (process* form forms environment) + (let recur ((form form) (forms forms)) + (receive (expansion bits) (process form environment) + (if (pair? forms) + (receive (tail bits*) (recur (car forms) (cdr forms)) + (values `(,(close-syntax 'APPEND environment) ,expansion ,tail) + (+ bits bits*))) + (values expansion bits))))) + +(define (process form environment) + (if (not (pair? form)) + (error "Invalid instruction syntax:" form)) + (case (car form) + ((IF) (process-if form environment)) + ((BITS) (process-fixed form environment)) + ((VARIABLE-WIDTH) (process-variable form environment)) + ((MACRO) (process-macro form environment)) + (else (error "Unknown instruction syntax:" form)))) + +(define (process-if form environment) + (let ((condition (cadr form)) + (consequent (caddr form)) + (alternative (cadddr form))) + (receive (con-exp con-bits) (process consequent environment) + (receive (alt-exp alt-bits) (process alternative environment) + (assert (eqv? con-bits alt-bits)) + (values `(,(close-syntax 'IF environment) ,condition ,con-exp ,alt-exp) + con-bits))))) + +(define (process-fixed form environment) + (receive (expansion bits) (expand-fields (cdr form) environment) + (values (optimize-group-syntax expansion #f environment) bits))) + +(define (process-variable form environment) + (let ((variable (cadr form)) + (expression (caddr form)) + (clauses (cdddr form))) + (let ((options (map (process-variable-clause environment) clauses))) + (let ((expression + (variable-width-expression-syntaxer variable + expression + environment + options))) + (values expression #f))))) + +(define ((process-variable-clause environment) clause) + (let ((range (car clause)) + (forms (cdr clause))) + (receive (expansion bits) (process* (car forms) (cdr forms) environment) + (assert bits "Variable within variable prohibited!") + (assert (zero? (remainder bits 32)) "Wrong number of bits!") + `(,expansion ,bits ,range)))) + +(define (process-macro form environment) + (let ((width (cadr form)) + (expansion (caddr form))) + (values ;; XXX Check the width here. Check for cycles. + `((,(close-syntax 'INSTRUCTION-LOOKUP environment) + (,(close-syntax 'QUASIQUOTE environment) + ,expansion))) + width))) + +(define (expand-fields fields environment) + (let loop ((fields fields) (elements '()) (bits 0)) + (if (pair? fields) + (receive (element1 bits1) (expand-field (car fields) environment) + (loop (cdr fields) (cons element1 elements) (+ bits1 bits))) + (values (reverse! elements) bits)))) + +(define (expand-field field environment) + (let ((bits (car field)) + (expression (cadr field)) + (coercion (if (pair? (cddr field)) (caddr field) 'UNSIGNED))) + (values + (case coercion + ((BLOCK-OFFSET) + `(,(close-syntax 'LIST environment) 'BLOCK-OFFSET ,expression)) + (else + (integer-syntaxer expression environment coercion bits))) + bits))) diff --git a/src/compiler/machines/aarch64/instr.scm b/src/compiler/machines/aarch64/instr1.scm similarity index 52% rename from src/compiler/machines/aarch64/instr.scm rename to src/compiler/machines/aarch64/instr1.scm index d4b328495..ac30505f6 100644 --- a/src/compiler/machines/aarch64/instr.scm +++ b/src/compiler/machines/aarch64/instr1.scm @@ -24,137 +24,33 @@ USA. |# -;;;; AArch Instruction Set +;;;; AArch64 Instruction Set, part 1 ;;; package: (compiler lap-syntaxer) (declare (usual-integrations)) -;;; Idea for branch tensioning: in every @PCR, allow an optional -;;; temporary register, like (@PCR