From c35f5f8953541064975e33e72517f6a35dfd083b Mon Sep 17 00:00:00 2001 From: Stephen Adams Date: Mon, 18 Nov 1996 21:19:35 +0000 Subject: [PATCH] Used macros to name all machine registers. This allows the integer syntax and the %r syntax to be used. Currently, the syntax is chosen according to the compiler. This should really be orthogonal. -DGCC integer syntax -DHPC %r syntax --- v8/src/microcode/cmpauxmd/hppa.m4 | 1779 +++++++++++++++-------------- 1 file changed, 924 insertions(+), 855 deletions(-) diff --git a/v8/src/microcode/cmpauxmd/hppa.m4 b/v8/src/microcode/cmpauxmd/hppa.m4 index c7eea0de1..06c0efbf3 100644 --- a/v8/src/microcode/cmpauxmd/hppa.m4 +++ b/v8/src/microcode/cmpauxmd/hppa.m4 @@ -1,6 +1,6 @@ changecom(`;');;; -*-Midas-*- ;;; -;;; $Id: hppa.m4,v 1.41 1996/08/12 23:13:25 cph Exp $ +;;; $Id: hppa.m4,v 1.42 1996/11/18 21:19:35 adams Exp $ ;;; ;;; Copyright (c) 1989-1996 Massachusetts Institute of Technology ;;; @@ -41,6 +41,14 @@ changecom(`;');;; -*-Midas-*- ;;;; code interface. See cmpint.txt, cmpint.c, cmpint-hppa.h, and ;;;; cmpgc.h for more documentation. ;;;; +;;;; M4 command line flags: +;;;; One of: +;;;; -DHPC Use parameter passing conventions for HP's C compiler +;;;; -DGCC Use parameter passing conventions for GNU cc +;;;; These also select the assembler syntax (HP registers use `%r', +;;;;; GNU uses just integers). +;;;; -DTYPECODE_LENGTH=6 +;;;; ;;;; NOTE: ;;;; Assumptions: ;;;; @@ -194,40 +202,98 @@ define(FLONUM_VECTOR_HEADER, eval((TC_NMV * (2 ** DATUM_LENGTH)) + 2)) define(SHARP_F, HEX(22000010)) ; Available from r5 define(SHARP_T, HEX(23000000)) ; Available via LDIL +;;;; Assembler syntax variations +;; +;; Machine registers are named `gr' `fpr' and `spr'. +;; + +define(use_percent_syntax,ifdef("HPC",1,0)) + +ifelse(use_percent_syntax,1," +define(gr0,%r0) define(gr1,%r1) define(gr2,%r2) +define(gr3,%r3) define(gr4,%r4) define(gr5,%r5) +define(gr6,%r6) define(gr7,%r7) define(gr8,%r8) +define(gr9,%r9) define(gr10,%r10) define(gr11,%r11) +define(gr12,%r12) define(gr13,%r13) define(gr14,%r14) +define(gr15,%r15) define(gr16,%r16) define(gr17,%r17) +define(gr18,%r18) define(gr19,%r19) define(gr20,%r20) +define(gr21,%r21) define(gr22,%r22) define(gr23,%r23) +define(gr24,%r24) define(gr25,%r25) define(gr26,%r26) +define(gr27,%r27) define(gr28,%r28) define(gr29,%r29) +define(gr30,%r30) define(gr31,%r31) +define(fpr0,%fr0) define(fpr1,%fr1) define(fpr2,%fr2) +define(fpr3,%fr3) define(fpr4,%fr4) define(fpr5,%fr5) +define(fpr6,%fr6) define(fpr7,%fr7) define(fpr8,%fr8) +define(fpr9,%fr9) define(fpr10,%fr10) define(fpr11,%fr11) +define(fpr12,%fr12) define(fpr13,%fr13) define(fpr14,%fr14) +define(fpr15,%fr15) define(fpr16,%fr16) define(fpr17,%fr17) +define(fpr18,%fr18) define(fpr19,%fr19) define(fpr20,%fr20) +define(fpr21,%fr21) define(fpr22,%fr22) define(fpr23,%fr23) +define(fpr24,%fr24) define(fpr25,%fr25) define(fpr26,%fr26) +define(fpr27,%fr27) define(fpr28,%fr28) define(fpr29,%fr29) +define(fpr30,%fr30) define(fpr31,%fr31) +define(spr4,%sr4) define(spr5,%sr5)", + +"define(gr0,0) define(gr1,1) define(gr2,2) define(gr3,3) define(gr4,4) +define(gr5,5) define(gr6,6) define(gr7,7) define(gr8,8) define(gr9,9) +define(gr10,10) define(gr11,11) define(gr12,12) define(gr13,13) define(gr14,14) +define(gr15,15) define(gr16,16) define(gr17,17) define(gr18,18) define(gr19,19) +define(gr20,20) define(gr21,21) define(gr22,22) define(gr23,23) define(gr24,24) +define(gr25,25) define(gr26,26) define(gr27,27) define(gr28,28) define(gr29,29) +define(gr30,30) define(gr31,31) +define(fpr0,0) define(fpr1,1) define(fpr2,2) +define(fpr3,3) define(fpr4,4) define(fpr5,5) +define(fpr6,6) define(fpr7,7) define(fpr8,8) +define(fpr9,9) define(fpr10,10) define(fpr11,11) +define(fpr12,12) define(fpr13,13) define(fpr14,14) +define(fpr15,15) define(fpr16,16) define(fpr17,17) +define(fpr18,18) define(fpr19,19) define(fpr20,20) +define(fpr21,21) define(fpr22,22) define(fpr23,23) +define(fpr24,24) define(fpr25,25) define(fpr26,26) +define(fpr27,27) define(fpr28,28) define(fpr29,29) +define(fpr30,30) define(fpr31,31) +define(spr4,4) define(spr5,5)") + +;; The `indexed' macro is used for building indexed addressing specifiers. +;; the problem is that if a register name is a macro it eats the +;; following text in parentheses. Using indexed(gr5,(0,gr6)) instead +;; of gr5(0,gr6) fixes the problem. +define(indexed,$1$2) + ;; Temporary registers for register-preserving utilities -define(gt1,26) -define(gt2,25) -define(gt3,28) -define(gt4,29) -define(ft1,4) -define(ft2,5) +define(gt1,gr26) +define(gt2,gr25) +define(gt3,gr28) +define(gt4,gr29) +define(ft1,fpr4) +define(ft2,fpr5) ;; Scheme register assignments -define(rs_val,2) ;not really - -define(rs_ble,3) -define(rs_regblock,4) -define(rs_false,5) -define(rs_quad,5) -define(rs_empty_list,18) -define(rs_continuation,19) -define(rs_memtop,20) -define(rs_free,21) -define(rs_stack,22) -define(rs_closure,25) +define(rs_val,gr2) ;not really + +define(rs_ble,gr3) +define(rs_regblock,gr4) +define(rs_false,gr5) +define(rs_quad,gr5) +define(rs_empty_list,gr18) +define(rs_continuation,gr19) +define(rs_memtop,gr20) +define(rs_free,gr21) +define(rs_stack,gr22) +define(rs_closure,gr25) ;; register argument homes: 2 6 7 8 9 10 11 12 13 14 15 16 17 23 24 define(ARGUMENT_REGISTERS,15) ;;define(ARGUMENT_REGISTERS,3) -define(rs_arg1,2) define(rs_arg2,6) -define(rs_arg3,7) define(rs_arg4,8) -define(rs_arg5,9) define(rs_arg6,10) -define(rs_arg7,11) define(rs_arg8,12) -define(rs_arg9,13) define(rs_arg10,14) -define(rs_arg11,15) define(rs_arg12,16) -define(rs_arg13,17) define(rs_arg14,23) -define(rs_arg15,24) +define(rs_arg1,gr2) define(rs_arg2,gr6) +define(rs_arg3,gr7) define(rs_arg4,gr8) +define(rs_arg5,gr9) define(rs_arg6,gr10) +define(rs_arg7,gr11) define(rs_arg8,gr12) +define(rs_arg9,gr13) define(rs_arg10,gr14) +define(rs_arg11,gr15) define(rs_arg12,gr16) +define(rs_arg13,gr17) define(rs_arg14,gr23) +define(rs_arg15,gr24) ;; scheme intepreter register block offsets, as in const.h but with block ;; indexes (i.e. word offsets) adjusted to byte offsets (i.e. *4) @@ -247,20 +313,20 @@ define(REGBLOCK_STACK_GUARD,44(0,rs_regblock)) define(REGBLOCK_INT_CODE,48(0,rs_regblock)) define(REGBLOCK_REFLECT_TO_INTERFACE,52(0,rs_regblock)) define(REGBLOCK_EMPTY_LIST,56(0,rs_regblock)) ; allows '() = #F compatability -define(REGBLOCK_COMPILER_PSEUDOREGS,64(rs_regblock)) +define(REGBLOCK_COMPILER_PSEUDOREGS,64(0,rs_regblock)) ;; C register assignments -define(rc_return_address,2) -define(rc_arg1,26) -define(rc_arg2,25) -define(rc_arg3,24) -define(rc_arg4,23) +define(rc_return_address,gr2) +define(rc_arg1,gr26) +define(rc_arg2,gr25) +define(rc_arg3,gr24) +define(rc_arg4,gr23) -define(rc_static_area,27) -define(rc_val,28) -define(rc_val_2,29) -define(rc_stack,30) +define(rc_static_area,gr27) +define(rc_val,gr28) +define(rc_val_2,gr29) +define(rc_stack,gr30) ;; Register assignments for generic arithmetic @@ -274,6 +340,7 @@ define(ENTRY_TO_ADDRESS, "") ;; "DEP rs_quad,TC_START,TC_LENGTH,$1")) +ifdef("HPC", "", ifdef("GCC", "", "Unknown C compiler: (not GCC or HPC)")) ;;define(C_FRAME_SIZE, ;; ifdef("HPC", 112, ;; ifdef("GCC", 120, @@ -289,6 +356,8 @@ define(INT_BIT_GC, 30) .SPACE $TEXT$ .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY + .LEVEL 1.1 + C_to_interface ;; rc_arg1 = compiled entry point ;; @@ -297,25 +366,25 @@ C_to_interface .ENTRY ;; Save C callee-saves registers on C stack STW rc_return_address,-20(0,rc_stack) ; Save return address - STWM 3,eval(C_FRAME_SIZE)(rc_stack) ; Save first reg, - STW 4,-108(rc_stack) ; and allocate frame - STW 5,-104(rc_stack) ; Save the other regs.. - STW 6,-100(rc_stack) - STW 7,-96(rc_stack) - STW 8,-92(rc_stack) - STW 9,-88(rc_stack) - STW 10,-84(rc_stack) - STW 11,-80(rc_stack) - STW 12,-76(rc_stack) - STW 13,-72(rc_stack) - STW 14,-68(rc_stack) - STW 15,-64(rc_stack) - STW 16,-60(rc_stack) - STW 17,-56(rc_stack) - STW 18,-52(rc_stack) + STWM gr3,eval(C_FRAME_SIZE)(rc_stack) ; Save first reg, + STW gr4,-108(rc_stack) ; and allocate frame + STW gr5,-104(rc_stack) ; Save the other regs.. + STW gr6,-100(rc_stack) + STW gr7,-96(rc_stack) + STW gr8,-92(rc_stack) + STW gr9,-88(rc_stack) + STW gr10,-84(rc_stack) + STW gr11,-80(rc_stack) + STW gr12,-76(rc_stack) + STW gr13,-72(rc_stack) + STW gr14,-68(rc_stack) + STW gr15,-64(rc_stack) + STW gr16,-60(rc_stack) + STW gr17,-56(rc_stack) + STW gr18,-52(rc_stack) ADDIL L'Registers-$global$,rc_static_area - LDO R'Registers-$global$(1),rs_regblock ; Setup Regs + LDO R'Registers-$global$(gr1),rs_regblock ; Setup Regs ;; The Quad mask is the low bits of the SHARP_F LDIL L'SHARP_F,rs_false ;; ADDI avoids assember bug with: LDO R'SHARP_F(rs_false),rs_false @@ -325,7 +394,7 @@ C_to_interface ep_interface_to_scheme ;; LDW REGBLOCK_VAL,rs_arg1 ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - LDW R'Ext_Stack_Pointer-$global$(1),rs_stack + LDW R'Ext_Stack_Pointer-$global$(gr1),rs_stack ;; The Scheme stack holds: a count of actual parameters, that number of ;; actual parameters, a continuation. @@ -398,10 +467,10 @@ ep_interface_to_scheme_2 ;; A (modified) copy of this code is part of invoke_primitive LDW REGBLOCK_MEMTOP,rs_memtop ADDIL L'Free-$global$,rc_static_area - LDW R'Free-$global$(1),rs_free + LDW R'Free-$global$(gr1),rs_free .CALL RTNVAL=GR ; out=28 - BLE 0(5,rc_arg1) ; Invoke entry point... - LDO scheme_to_interface_ble-trampoline_to_interface(31),rs_ble + BLE 0(spr5,rc_arg1) ; Invoke entry point... + LDO scheme_to_interface_ble-trampoline_to_interface(gr31),rs_ble ; with rs_ble = scheme_to_interface_ble ;; The compiler knows offsets from scheme_to_interface_ble including @@ -412,7 +481,7 @@ trampoline_to_interface ;; On entry: r31 points into trampoline ;; r28 is the utility index ;; Note that we must preserve rc_arg[2-4] - LDW -3(31),29 ; get trampoline arg count + LDW -3(gr31),gr29 ; get trampoline arg count bkpt_hook_to_interface ;; On entry: r31 points to trampoline or breakpointed procedure/closure @@ -423,40 +492,40 @@ bkpt_hook_to_interface ADDI 4,rs_continuation,rs_continuation ; on return skip ADDI insn: scheme_to_interface_ble - ADDI 4,31,31 ; Skip over format word ... + ADDI 4,gr31,gr31 ; Skip over format word ... - COPY 31,rc_arg1 - DEP 0,31,2,rc_arg1 ; clear privilege bits + COPY gr31,rc_arg1 + DEPI 0,31,2,rc_arg1 ; clear privilege bits scheme_to_interface ;;STW rs_val,REGBLOCK_VAL ADDIL L'hppa_utility_table-$global$,rc_static_area - LDW R'hppa_utility_table-$global$(1),29 + LDW R'hppa_utility_table-$global$(gr1),gr29 ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - LDWX,S 28(0,29),29 ; Find handler - STW rs_stack,R'Ext_Stack_Pointer-$global$(1) + LDWX,S indexed(gr28,(0,gr29)),gr29 ; Find handler + STW rs_stack,R'Ext_Stack_Pointer-$global$(gr1) ADDIL L'Free-$global$,rc_static_area - STW rs_free,R'Free-$global$(1) ; Update free + STW rs_free,R'Free-$global$(gr1) ; Update free ifelse(ASM_DEBUG,1,"ADDIL L'interface_counter-$global$,rc_static_area - LDW R'interface_counter-$global$(1),21 - LDO 1(21),21 - STW 21,R'interface_counter-$global$(1) + LDW R'interface_counter-$global$(gr1),21 + LDO 1(gr21),gr21 + STW gr21,R'interface_counter-$global$(gr1) ADDIL L'interface_limit-$global$,rc_static_area - LDW R'interface_limit-$global$(1),22 - COMB,=,N 21,22,interface_break + LDW R'interface_limit-$global$(gr1),gr22 + COMB,=,N gr21,gr22,interface_break interface_proceed") ;; not 2.6.3 -;; ifdef("GCC", "LDO -116(rc_stack),28") +;; ifdef("GCC", "LDO -116(rc_stack),gr28") .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR,RTNVAL=GR - BLE 0(4,29) ; Call handler - COPY 31,2 ; Setup return address + BLE 0(spr4,gr29) ; Call handler + COPY gr31,gr2 ; Setup return address ;; not 2.6.3 -;; ifdef("GCC", "LDW -116(rc_stack),28 -;; LDW -112(rc_stack),29") - BV 0(28) ; Call receiver - COPY 29,rc_arg1 ; Setup entry point +;; ifdef("GCC", "LDW -116(rc_stack),gr28 +;; LDW -112(rc_stack),gr29") + BV 0(gr28) ; Call receiver + COPY gr29,rc_arg1 ; Setup entry point ;; This sequence of NOPs is provided to allow for reassembly of the ;; sequence that appears above using different ifdefs without having @@ -486,23 +555,23 @@ ep_scheme_hooks_low hook_jump_table ; scheme_to_interface + 100 store_closure_code_hook B store_closure_code+4 - LDIL L'0x23400000,20 ; LDIL opcode and register + LDIL L'0x23400000,gr20 ; LDIL opcode and register store_closure_entry_hook B store_closure_entry+4 - DEP 0,31,2,1 ; clear PC protection bits + DEPI 0,31,2,gr1 ; clear PC protection bits multiply_fixnum_hook B multiply_fixnum+4 - STW 26,0(0,rs_free) + STW gr26,0(0,rs_free) fixnum_quotient_hook B fixnum_quotient+4 - STW 25,4(0,rs_free) ; yes, this is arg2 + STW gr25,4(0,rs_free) ; yes, this is arg2 fixnum_remainder_hook B fixnum_remainder+4 - STWM 29,-4(0,rs_stack) ; Preserve gr29 + STWM gr29,-4(0,rs_stack) ; Preserve gr29 fixnum_lsh_hook B fixnum_lsh+4 @@ -558,47 +627,47 @@ generic_negative_hook shortcircuit_apply_hook B shortcircuit_apply+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_1_hook B shortcircuit_apply_1+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_2_hook B shortcircuit_apply_2+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_3_hook B shortcircuit_apply_3+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_4_hook B shortcircuit_apply_4+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_5_hook B shortcircuit_apply_5+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_6_hook B shortcircuit_apply_6+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_7_hook B shortcircuit_apply_7+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 shortcircuit_apply_8_hook B shortcircuit_apply_8+4 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 stack_and_interrupt_check_hook B stack_and_interrupt_check+4 - LDW REGBLOCK_STACK_GUARD,25 + LDW REGBLOCK_STACK_GUARD,gr25 invoke_primitive_hook B invoke_primitive+4 - DEPI 0,31,2,31 ; clear privilege bits + DEPI 0,31,2,gr31 ; clear privilege bits vector_cons_hook B vector_cons+4 @@ -614,83 +683,83 @@ floating_vector_cons_hook flonum_sin_hook B flonum_sin+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_cos_hook B flonum_cos+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_tan_hook B flonum_tan+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_asin_hook B flonum_asin+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_acos_hook B flonum_acos+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_atan_hook B flonum_atan+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_exp_hook B flonum_exp+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_log_hook B flonum_log+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_truncate_hook B flonum_truncate+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_ceiling_hook B flonum_ceiling+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_floor_hook B flonum_floor+4 - COPY rs_stack,17 + COPY rs_stack,gr17 flonum_atan2_hook B flonum_atan2+4 - COPY rs_stack,17 + COPY rs_stack,gr17 compiled_code_bkpt_hook ; hook 44 (offset 451 + 1) B compiled_code_bkpt+4 - LDO -8(31),31 + LDO -8(gr31),gr31 compiled_closure_bkpt_hook ; hook 45 (offset 451 + 9) B compiled_closure_bkpt+4 - LDO -12(31),31 + LDO -12(gr31),gr31 copy_closure_pattern_hook B copy_closure_pattern+4 - LDW -3(0,31),29 ; offset + LDW -3(0,gr31),gr29 ; offset copy_multiclosure_pattern_hook B copy_multiclosure_pattern+4 - LDW -3(0,31),29 ; offset + LDW -3(0,gr31),gr29 ; offset closure_entry_bkpt_hook ; hook 48 (offset 451 + 33) B closure_entry_bkpt+4 - LDO -8(31),31 ; bump back to entry point + LDO -8(gr31),gr31 ; bump back to entry point new_procedure_interrupt_hook ; hook 49 B new_procedure_interrupt+4 - LDW -3(0,31),20 ; return address offset + LDW -3(0,gr31),gr20 ; return address offset new_continuation_interrupt_hook ; hook 50 B new_continuation_interrupt+4 - LDW -3(0,31),20 ; return address offset + LDW -3(0,gr31),gr20 ; return address offset new_closure_interrupt_hook B new_interrupt_common ; hook 51 - COPY rs_closure,20 + COPY rs_closure,gr20 generic_quotient_hook ; hook 52 B generic_quotient+4 @@ -706,10 +775,10 @@ interpreter_call_hook NOP profile_count_hook - LDW -7(0,31),1 ; hook 55 - ADDI 1,1,1 - BE 0(5,31) ; hook 56 - STW 1,-7(0,31) + LDW -7(0,gr31),gr1 ; hook 55 + ADDI 1,gr1,gr1 + BE 0(spr5,gr31) ; hook 56 + STW gr1,-7(0,gr31) set_interrupt_enables_hook B set_interrupt_enables ; hook 57 @@ -755,7 +824,7 @@ no_hook ifelse(ASM_DEBUG,1,"interface_break - COMB,= 21,22,interface_break + COMB,= gr21,gr22,interface_break NOP B,N interface_proceed") @@ -780,18 +849,18 @@ ifelse(ASM_DEBUG,1,"interface_break ;; ;; Uses: 1, rs_empty_list -define(pa_count,29) +define(pa_count,gr29) define(pa_link,rs_continuation) define(pa_ptr,rs_empty_list) ; auxillary pointer -define(pa_tmp,1) ; auxillary pointer +define(pa_tmp,gr1) ; auxillary pointer push_arg_registers - SUBI,>= ARGUMENT_REGISTERS,pa_count,1 ; complement - LDI 0,1 - ;; complement of number of regs is in 1, from ARGUMENT_REGISTERS down to + SUBI,>= ARGUMENT_REGISTERS,pa_count,gr1 ; complement + LDI 0,gr1 + ;; complement of number of regs in r1, from ARGUMENT_REGISTERS down to ;; 0 inclusive - BLR 1,0 + BLR gr1,gr0 NOP STWM rs_arg15,-4(0,rs_stack) @@ -847,17 +916,17 @@ pa_reverse_finished store_closure_entry ;; -;; On arrival, 31 has a return address and 1 contains the address to +;; On arrival, r31 has a return address and r1 contains the address to ;; which the closure should jump with pc protection bits. -;; 26 contains the format/gc-offset word for this entry. +;; r26 contains the format/gc-offset word for this entry. ;; - DEP 0,31,2,1 ; clear PC protection bits - STWM 26,4(0,rs_free) ; move format long to heap + DEPI 0,31,2,gr1 ; clear PC protection bits + STWM gr26,4(0,rs_free) ; move format long to heap ;; fall through to store_closure_code store_closure_code ;; -;; On arrival, 31 has a return address and 1 contains the address to +;; On arrival, r31 has a return address and r1 contains the address to ;; which the closure should jump. The appropriate instructions (LDIL ;; and BLE and SUBI) are pushed on the heap. ;; Important: @@ -871,74 +940,76 @@ store_closure_code ;; The SYNC is assumed to be separated by at least 7 instructions from ;; the first execution of the new instructions. ;; - LDIL L'0x23400000,20 ; LDIL opcode and register - EXTRU 1,0,1,5 - DEP 5,31,1,20 - EXTRU 1,11,11,5 - DEP 5,30,11,20 - EXTRU 1,13,2,5 - DEP 5,17,2,20 - EXTRU 1,18,5,5 - DEP 5,15,5,20 - STW 20,0(0,rs_free) ; Store LDIL instruction - LDIL L'0xe7406000,20 ; BLE opcode, register - LDO R'0xe7406000(20),20 ; and nullify - EXTRU 1,19,1,5 - DEP 5,29,1,20 - EXTRU 1,29,10,5 - DEP 5,28,10,20 - STW 20,4(0,rs_free) ; Store BLE instruction - LDIL L'0xb7ff07e9,20 - LDO R'0xb7ff07e9(20),20 - STW 20,8(0,rs_free) ; Store ADDI instruction - LDI 12,20 + LDIL L'0x23400000,gr20 ; LDIL opcode and register + EXTRU gr1,0,1,gr5 + DEP gr5,31,1,gr20 + EXTRU gr1,11,11,gr5 + DEP gr5,30,11,gr20 + EXTRU gr1,13,2,gr5 + DEP gr5,17,2,gr20 + EXTRU gr1,18,5,gr5 + DEP gr5,15,5,gr20 + STW gr20,0(0,rs_free) ; Store LDIL instruction + LDIL L'0xe7406000,gr20 ; BLE opcode, register + LDO R'0xe7406000(gr20),gr20 ; and nullify + EXTRU gr1,19,1,gr5 + DEP gr5,29,1,gr20 + EXTRU gr1,29,10,gr5 + DEP gr5,28,10,gr20 + STW gr20,4(0,rs_free) ; Store BLE instruction + LDIL L'0xb7ff07e9,gr20 + LDO R'0xb7ff07e9(gr20),gr20 + STW gr20,8(0,rs_free) ; Store ADDI instruction + LDI 12,gr20 FDC 0(0,rs_free) ; flush 1st inst. from D-cache - FDC 20(0,rs_free) ; flush last inst. from D-cache + FDC indexed(gr20,(0,rs_free)) ; flush last inst. from D-cache SYNC - FIC,M 20(5,rs_free) ; flush 1st inst. from I-cache + FIC,M indexed(gr20,(spr5,rs_free)) ; flush 1st inst. from I-cache SYNC ;; Restore register 5 - LDIL L'SHARP_F,5 - ; LDO R'SHARP_F(5),5 ; Assembler bug! - ADDI R'SHARP_F,5,5 - BE 0(5,31) ; Return + LDIL L'SHARP_F,gr5 + ; LDO R'SHARP_F(gr5),gr5 ; Assembler bug! + ADDI R'SHARP_F,gr5,gr5 + BE 0(spr5,gr31) ; Return LDW REGBLOCK_MEMTOP,rs_memtop ;restore multiply_fixnum ;; untagged integer version -;; On arrival, 31 has a return address and 26 and 25 have the fixnum arguments. + +;; On arrival, r31 has a return address and r26 and r25 have the fixnum +;; arguments. ;; - STW 26,0(0,rs_free) ; copy in jump table - STW 25,4(0,rs_free) - ZDEPI 1,TC_LENGTH-1,1,26 ; FIXNUM_LIMIT - FLDWS 0(0,rs_free),4 - FLDWS 4(0,rs_free),5 - STW 26,8(0,rs_free) ; FIXNUM_LIMIT - FCNVXF,SGL,DBL 4,4 ; arg1 - FCNVXF,SGL,DBL 5,5 ; arg2 - FMPY,DBL 4,5,4 - FLDWS 8(0,rs_free),5 ; FIXNUM_LIMIT - FCNVXF,SGL,DBL 5,5 ; FIXNUM_LIMIT - COPY 0,25 ; signal no overflow - FCMP,DBL,!>= 4,5 ; result too large? + STW gr26,0(0,rs_free) ; copy in jump table + STW gr25,4(0,rs_free) + ZDEPI 1,TC_LENGTH-1,1,gr26 ; FIXNUM_LIMIT + FLDWS 0(0,rs_free),fpr4 + FLDWS 4(0,rs_free),fpr5 + STW gr26,8(0,rs_free) ; FIXNUM_LIMIT + FCNVXF,SGL,DBL fpr4,fpr4 ; arg1 + FCNVXF,SGL,DBL fpr5,fpr5 ; arg2 + FMPY,DBL fpr4,fpr5,fpr4 + FLDWS 8(0,rs_free),fpr5 ; FIXNUM_LIMIT + FCNVXF,SGL,DBL fpr5,fpr5 ; FIXNUM_LIMIT + COPY gr0,gr25 ; signal no overflow + FCMP,DBL,!>= fpr4,fpr5 ; result too large? FTEST B,N multiply_fixnum_ovflw - FSUB,DBL 0,5,5 - FCMP,DBL,!< 4,5 ; result too small? + FSUB,DBL fpr0,fpr5,fpr5 + FCMP,DBL,!< fpr4,fpr5 ; result too small? FTEST B,N multiply_fixnum_ovflw - FCNVFXT,DBL,SGL 4,5 - FSTWS 5,0(0,rs_free) ; result - BE 0(5,31) ; return - LDW 0(0,rs_free),26 + FCNVFXT,DBL,SGL fpr4,fpr5 + FSTWS fpr5,0(0,rs_free) ; result + BE 0(spr5,gr31) ; return + LDW 0(0,rs_free),gr26 ;; multiply_fixnum_ovflw - LDO 1(0),25 ; signal overflow - BE 0(5,31) ; return - LDI 0,26 ; unused return `product' + LDI 1,gr25 ; signal overflow + BE 0(spr5,gr31) ; return + LDI 0,gr26 ; unused return `product' @@ -949,28 +1020,28 @@ fixnum_quotient ;; divisor is -1 and the dividend is the most negative fixnum, ;; producing the most positive fixnum plus 1. ;; - STW 25,4(0,rs_free) ; arg2 - COMB,= 0,25,fixnum_quotient_ovflw - STW 26,0(0,rs_free) - ZDEPI 1,TC_LENGTH-1,1,26 ; FIXNUM_LIMIT - FLDWS 0(0,rs_free),4 - FLDWS 4(0,rs_free),5 - FCNVXF,SGL,DBL 4,4 ; arg1 - FCNVXF,SGL,DBL 5,5 ; arg2 - FDIV,DBL 4,5,4 - STW 25,0(0,rs_free) ; FIXNUM_LIMIT - FCNVFXT,DBL,SGL 4,5 - FSTWS 5,4(0,rs_free) ; result - FLDWS 0(0,rs_free),5 ; FIXNUM_LIMIT - FCNVXF,SGL,DBL 5,5 - FCMP,DBL,!>= 4,5 ; result too large? - LDW 4(0,rs_free),26 - COPY 0,25 ; signal no overflow + STW gr25,4(0,rs_free) ; arg2 + COMB,= 0,gr25,fixnum_quotient_ovflw + STW gr26,0(0,rs_free) + ZDEPI 1,TC_LENGTH-1,1,gr26 ; FIXNUM_LIMIT + FLDWS 0(0,rs_free),fpr4 + FLDWS 4(0,rs_free),fpr5 + FCNVXF,SGL,DBL fpr4,fpr4 ; arg1 + FCNVXF,SGL,DBL fpr5,fpr5 ; arg2 + FDIV,DBL fpr4,fpr5,fpr4 + STW gr25,0(0,rs_free) ; FIXNUM_LIMIT + FCNVFXT,DBL,SGL fpr4,fpr5 + FSTWS fpr5,4(0,rs_free) ; result + FLDWS 0(0,rs_free),fpr5 ; FIXNUM_LIMIT + FCNVXF,SGL,DBL fpr5,fpr5 + FCMP,DBL,!>= fpr4,fpr5 ; result too large? + LDW 4(0,rs_free),gr26 + COPY gr0,gr25 ; signal no overflow FTEST ;; fixnum_quotient_ovflw - LDO 1(0),25 ; signal overflow - BE 0(5,31) ; return + LDI 1,gr25 ; signal overflow + BE 0(spr5,gr31) ; return NOP @@ -1009,49 +1080,49 @@ fixnum_quotient_ovflw ;;;; ;;fixnum_remainder_done ;; ZDEP 1,FIXNUM_POS,FIXNUM_LENGTH,26 ; make into fixnum -;; BE 0(5,31) ; return +;; BE 0(spr5,31) ; return ;; COPY 0,25 ; signal no overflow ;;;; ;;fixnum_remainder_ovflw -;; BE 0(5,31) ; return +;; BE 0(spr5,31) ; return ;; LDO 1(0),25 ; signal overflow fixnum_remainder ;; -;; On arrival, 31 has a return address and 26 and 25 have the fixnum +;; On arrival, r31 has a return address and r26 and r25 have the fixnum ;; arguments. ;; Remainder can overflow only if arg2 = 0. ;; - STWM 29,-4(0,rs_stack) ; Preserve gr29 - COMB,=,N 0,25,fixnum_remainder_ovflw - STWM 31,-4(0,rs_stack) ; Preserve ret. add. - STWM 26,-4(0,rs_stack) ; Preserve arg1 + STWM gr29,-4(0,rs_stack) ; Preserve gr29 + COMB,=,N gr0,gr25,fixnum_remainder_ovflw + STWM gr31,-4(0,rs_stack) ; Preserve ret. add. + STWM gr26,-4(0,rs_stack) ; Preserve arg1 .CALL ;in=25,26;out=29; (MILLICALL) - BL $$remI,31 - STWM 25,-4(0,rs_stack) ; Preserve arg2 + BL $$remI,gr31 + STWM gr25,-4(0,rs_stack) ; Preserve arg2 ;; - LDWM 4(0,rs_stack),25 ; Restore arg2 - LDWM 4(0,rs_stack),26 ; Restore arg1 - XOR,< 26,29,0 ; Skip if signs != + LDWM 4(0,rs_stack),gr25 ; Restore arg2 + LDWM 4(0,rs_stack),gr26 ; Restore arg1 + XOR,< gr26,gr29,gr0 ; Skip if signs != B,N fixnum_remainder_done - COMB,=,N 0,29,fixnum_remainder_done - XOR,< 26,25,0 - ADD,TR 29,25,29 ; setup result - SUB 29,25,29 + COMB,=,N gr0,gr29,fixnum_remainder_done + XOR,< gr26,gr25,gr0 + ADD,TR gr29,gr25,gr29 ; setup result + SUB gr29,gr25,gr29 ;; fixnum_remainder_done - COPY 29,26 ; make into fixnum - LDWM 4(0,rs_stack),31 ; Restore ret. add. - COPY 0,25 ; signal no overflow - BE 0(5,31) ; return - LDWM 4(0,rs_stack),29 ; Restore gr29 + COPY gr29,gr26 ; make into fixnum + LDWM 4(0,rs_stack),gr31 ; Restore ret. add. + COPY gr0,gr25 ; signal no overflow + BE 0(spr5,gr31) ; return + LDWM 4(0,rs_stack),gr29 ; Restore gr29 ;; fixnum_remainder_ovflw - LDO 1(0),25 ; signal overflow - COPY 0,26 ; bogus return value - BE 0(5,31) ; return - LDWM 4(0,rs_stack),29 ; Restore gr29 + LDI 1,gr25 ; signal overflow + COPY gr0,gr26 ; bogus return value + BE 0(spr5,gr31) ; return + LDWM 4(0,rs_stack),gr29 ; Restore gr29 fixnum_lsh @@ -1060,26 +1131,26 @@ fixnum_lsh ;; If arg2 is negative, it is a right shift, otherwise a left shift. ;; NOP - COMB,<,N 0,25,fixnum_lsh_positive + COMB,<,N gr0,gr25,fixnum_lsh_positive ;; Shifting by a non-positive amount: we want to right shift - SUB 0,25,25 ; negate, for right shift - COMICLR,> FIXNUM_LENGTH,25,0 - COPY 0,26 - MTSAR 25 - VSHD 0,26,26 ; shift right - BE 0(5,31) - COPY 0,25 + SUB gr0,gr25,gr25 ; negate, for right shift + COMICLR,> FIXNUM_LENGTH,gr25,gr0 + COPY gr0,gr26 + MTSAR gr25 + VSHD gr0,gr26,gr26 ; shift right + BE 0(spr5,gr31) + COPY gr0,gr25 ;; fixnum_lsh_positive ;; Shifting by a positive amount: we want to left shift - SUBI,> 32,25,25 ; shift amount for right shift - COPY 0,26 ; shift left completely - MTSAR 25 - VSHD 26,0,26 ; shift right (32 - arg2) - EXTRS 26,31,FIXNUM_LENGTH,26 ; normalize fixnum - BE 0(5,31) ; return - COPY 0,25 ; signal no overflow + SUBI,> 32,gr25,gr25 ; shift amount for right shift + COPY gr0,gr26 ; shift left completely + MTSAR gr25 + VSHD gr26,gr0,gr26 ; shift right (32 - arg2) + EXTRS gr26,31,FIXNUM_LENGTH,gr26 ; normalize fixnum + BE 0(spr5,gr31) ; return + COPY gr0,gr25 ; signal no overflow ;;;; Generic arithmetic utilities. ;;; @@ -1113,7 +1184,7 @@ define(FLONUM_RESULT, STWM gt3,4(0,rs_free) ; vector header DEPI TC_FLONUM,TC_START,TC_LENGTH,rs_val ; tag pointer to vector as flonum ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) ; return! + BLE 0(spr5,gen_continuation) ; return! FSTDS,MA $1,8(0,rs_free)]) ; store floating data ;; Same idea for flonum comparisons: @@ -1124,7 +1195,7 @@ define(GENERIC_BOOLEAN_RESULT, FTEST COPY rs_false,rs_val ENTRY_TO_ADDRESS(gen_continuation) - BLE,N 0(5,gen_continuation)]) ; return! + BLE,N 0(spr5,gen_continuation)]) ; return! define(define_generic_binary, [generic_$1 @@ -1170,7 +1241,7 @@ ifelse($4,NONE,[],[ $4 gen_arg1,gen_arg2,gt4 ; add/sub JUMP_NOT_FIXNUM_FORWARD(gt4,gt3,generic_$1_fail) ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) ; return! + BLE 0(spr5,gen_continuation) ; return! COPY gt4,rs_arg1]) generic_$1_fail ; ?? * ??, out of line @@ -1178,7 +1249,7 @@ generic_$1_fail ; ?? * ??, out of line STWM gen_continuation,-4(0,rs_stack) STWM gen_arg2,-4(0,rs_stack) STWM gen_arg1,-4(0,rs_stack) - BB,< 31,31,scheme_to_interface + BB,< gr31,31,scheme_to_interface LDI HEX($2),gt3 ; operation code BL,N do_preserve_2,gt1 NOP @@ -1255,7 +1326,7 @@ generic_times_fix_fix ; FIX * FIX FCNVFXT,DBL,SGL ft1,ft2 FSTWS ft2,0(0,rs_free) ; result ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) ; return with + BLE 0(spr5,gen_continuation) ; return with LDW 0(0,rs_free),rs_val generic_times_fail ; ?? * ??, out of line @@ -1263,7 +1334,7 @@ generic_times_fail ; ?? * ??, out of line STWM gen_continuation,-4(0,rs_stack) STWM gen_arg2,-4(0,rs_stack) STWM gen_arg1,-4(0,rs_stack) - BB,< 31,31,scheme_to_interface + BB,< gr31,31,scheme_to_interface LDI HEX(29),gt3 ; operation code BL,N do_preserve_2,gt1 NOP @@ -1273,7 +1344,7 @@ generic_times_fail ; ?? * ??, out of line generic_times_0_flo generic_times_flo_0 ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) ; return with + BLE 0(spr5,gen_continuation) ; return with LDI 0,rs_val ; fixnum 0 = exact 0 result define(define_generic_binary_predicate, @@ -1316,7 +1387,7 @@ generic_$1_fix_fix COMCLR,$3 gen_arg1,gen_arg2,0 COPY rs_false,gt3 ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) + BLE 0(spr5,gen_continuation) COPY gt3,rs_val generic_$1_fail ; ?? * ??, out of line @@ -1324,7 +1395,7 @@ generic_$1_fail ; ?? * ??, out of line STWM gen_continuation,-4(0,rs_stack) STWM gen_arg2,-4(0,rs_stack) STWM gen_arg1,-4(0,rs_stack) - BB,< 31,31,scheme_to_interface + BB,< gr31,31,scheme_to_interface LDI HEX($2),gt3 ; operation code BL,N do_preserve_2,gt1 NOP @@ -1350,13 +1421,13 @@ generic_$1_not_flo ADDI $4,gen_arg1,gt4 ; inc/dec JUMP_NOT_FIXNUM_FORWARD(gt4,gt3,generic_$1_fail) ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) ; return! + BLE 0(spr5,gen_continuation) ; return! COPY gt4,rs_arg1 generic_$1_fail STWM gen_continuation,-4(0,rs_stack) STWM gen_arg1,-4(0,rs_stack) - BB,< 31,31,scheme_to_interface + BB,< gr31,31,scheme_to_interface LDI HEX($2),gt3 ; operation code BL,N do_preserve_1,gt1 NOP @@ -1377,13 +1448,13 @@ generic_$1_not_flo COMCLR,$3 gen_arg1,0,0 COPY rs_false,gt3 ENTRY_TO_ADDRESS(gen_continuation) - BLE 0(5,gen_continuation) + BLE 0(spr5,gen_continuation) COPY gt3,rs_val generic_$1_fail STWM gen_continuation,-4(0,rs_stack) STWM gen_arg1,-4(0,rs_stack) - BB,< 31,31,scheme_to_interface + BB,< gr31,31,scheme_to_interface LDI HEX($2),gt3 ; operation code BL,N do_preserve_1,gt1 NOP @@ -1408,12 +1479,12 @@ define(define_generic_out_of_line, STWM gen_continuation,-4(0,rs_stack) STWM gen_arg2,-4(0,rs_stack) STWM gen_arg1,-4(0,rs_stack) - BB,< 31,31,scheme_to_interface - LDI HEX($2),28 ; operation code + BB,< gr31,31,scheme_to_interface + LDI HEX($2),gr28 ; operation code BL,N do_preserve_2,gt1 NOP B scheme_to_interface - LDI HEX($2),28 ; operation code]) + LDI HEX($2),gr28 ; operation code]) define_generic_out_of_line(quotient,37) define_generic_out_of_line(remainder,38) @@ -1423,25 +1494,25 @@ changequote(",") ;;; Procedure in r26, arity (for shortcircuit-apply) in r25. shortcircuit_apply - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 COMICLR,= TC_CCENTRY,gt4,0 B,N shortcircuit_apply_lose ENTRY_TO_ADDRESS(26) - LDB -3(0,26),gt3 ; procedure's frame-size - COMB,<>,N 25,gt3,shortcircuit_apply_lose - BLE,N 0(5,26) ; invoke procedure + LDB -3(0,gr26),gt3 ; procedure's frame-size + COMB,<>,N gr25,gt3,shortcircuit_apply_lose + BLE,N 0(spr5,gr26) ; invoke procedure changequote([,]) define(define_shortcircuit_fixed, [shortcircuit_apply_$1 - EXTRU 26,5,6,gt4 ; procedure type -> gt4 + EXTRU gr26,5,6,gt4 ; procedure type -> gt4 COMICLR,= TC_CCENTRY,gt4,0 B shortcircuit_apply_lose - LDI $1,25 ; NB: in delay slot of branch & skip dest. - ENTRY_TO_ADDRESS(26) - LDB -3(0,26),gt3 ; procedure's frame-size - COMB,<>,N 25,gt3,shortcircuit_apply_lose - BLE,N 0(5,26) ; invoke procedure]) + LDI $1,gr25 ; NB: in delay slot of branch & skip dest. + ENTRY_TO_ADDRESS(gr26) + LDB -3(0,gr26),gt3 ; procedure's frame-size + COMB,<>,N gr25,gt3,shortcircuit_apply_lose + BLE,N 0(spr5,gr26) ; invoke procedure]) changequote(",") define_shortcircuit_fixed(1) @@ -1454,12 +1525,12 @@ define_shortcircuit_fixed(7) define_shortcircuit_fixed(8) shortcircuit_apply_lose - WHEN_CCENTRY_TAGGED("DEP gt4,5,6,26") ; insert type back + WHEN_CCENTRY_TAGGED("DEP gt4,5,6,gr26") ; insert type back STWM rs_continuation,-4(0,rs_stack) BL push_arg_registers,rs_continuation - ADDI -1,25,29 + ADDI -1,gr25,gr29 B scheme_to_interface - LDI 0x14,28 + LDI 0x14,gr28 ;;; ;; On arrival, rs_continuation has a return address and rs_arg1 has the mask. @@ -1498,13 +1569,13 @@ set_interrupt_enables ;; else "Heap_Top". LDI -1,rs_memtop - AND,= rs_arg1,gt2,0 + AND,= rs_arg1,gt2,gr0 B set_interrupt_enables_1 ADDIL L'MemTop-$global$,rc_static_area BB,< rs_arg1,INT_BIT_GC,set_interrupt_enables_1 - LDW R'MemTop-$global$(1),rs_memtop + LDW R'MemTop-$global$(gr1),rs_memtop ADDIL L'Heap_Top-$global$,rc_static_area - LDW R'Heap_Top-$global$(1),rs_memtop + LDW R'Heap_Top-$global$(gr1),rs_memtop set_interrupt_enables_1 @@ -1514,48 +1585,48 @@ set_interrupt_enables_1 ADDIL L'Stack_Guard-$global$,rc_static_area STW rs_memtop,REGBLOCK_MEMTOP BB,< rs_arg1,INT_BIT_STACK_OVERFLOW,set_interrupt_enables_2 - LDW R'Stack_Guard-$global$(1),gt2 + LDW R'Stack_Guard-$global$(gr1),gt2 ADDIL L'Stack_Bottom-$global$,rc_static_area - LDW R'Stack_Bottom-$global$(1),gt2 + LDW R'Stack_Bottom-$global$(gr1),gt2 set_interrupt_enables_2 COPY gt1,rs_arg1 - BLE 0(5,rs_continuation) ; return! + BLE 0(spr5,rs_continuation) ; return! STW gt2,REGBLOCK_STACK_GUARD ;;; Return address in r31. r26 contains the offset from the return ;;; address to the interrupt invocation label. stack_and_interrupt_check - LDW REGBLOCK_STACK_GUARD,25 + LDW REGBLOCK_STACK_GUARD,gr25 LDW REGBLOCK_MEMTOP,rs_memtop ;;; ;;; If the Scheme stack pointer is <= Stack_Guard, then the stack has ;;; overflowed -- in which case we must signal a stack-overflow interrupt. - COMB,<=,N rs_stack,25,stack_and_interrupt_check_stack_overflow + COMB,<=,N rs_stack,gr25,stack_and_interrupt_check_stack_overflow ;;; ;;; If (Free >= MemTop), signal an interrupt. COMB,>=,N rs_free,rs_memtop,stack_and_interrupt_check_signal_interrupt ;;; ;;; Otherwise, return normally -- there's nothing to do. - BE 0(5,31) + BE 0(spr5,gr31) NOP stack_and_interrupt_check_stack_overflow - LDW REGBLOCK_INT_CODE,25 ; IntCode -> r25 - LDW REGBLOCK_INT_MASK,29 ; IntEnb -> r29 + LDW REGBLOCK_INT_CODE,gr25 ; IntCode -> r25 + LDW REGBLOCK_INT_MASK,gr29 ; IntEnb -> r29 ;;; ;;; Set the stack-overflow interrupt bit and write the interrupt word ;;; back out to memory. If the stack-overflow interrupt is disabled, ;;; skip forward to gc test. Otherwise, set MemTop to -1 and signal ;;; the interrupt. - DEPI 1,INT_BIT_STACK_OVERFLOW,1,25 - BB,>= 29,INT_BIT_STACK_OVERFLOW,stack_and_interrupt_check_no_overflow - STW 25,REGBLOCK_INT_CODE ; r25 -> IntCode - ADDI -1,0,rs_memtop ; -1 -> r20 + DEPI 1,INT_BIT_STACK_OVERFLOW,1,gr25 + BB,>= gr29,INT_BIT_STACK_OVERFLOW,stack_and_interrupt_check_no_overflow + STW gr25,REGBLOCK_INT_CODE ; r25 -> IntCode + LDI -1,rs_memtop ; -1 -> r20 STW rs_memtop,REGBLOCK_MEMTOP ;;; ;;; If (Free >= MemTop), signal an interrupt. @@ -1566,8 +1637,8 @@ stack_and_interrupt_check_no_overflow ;;; To signal the interrupt, add the interrupt invocation offset to ;;; the return address, then return normally. stack_and_interrupt_check_signal_interrupt - ADD 26,31,31 - BE 0(5,31) ; return + ADD gr26,gr31,gr31 + BE 0(spr5,gr31) ; return NOP ;;; These two are called differently from the old interrupt hooks. @@ -1578,86 +1649,86 @@ stack_and_interrupt_check_signal_interrupt new_continuation_interrupt - LDW -3(0,31),20 ; return address offset + LDW -3(0,gr31),gr20 ; return address offset COPY rs_false,rs_continuation ; bogus object to protect GC B new_interrupt_common - ADD 20,31,20 ; return address + ADD gr20,gr31,gr20 ; return address new_closure_interrupt B new_interrupt_common - COPY rs_closure,20 ; return address is closure + COPY rs_closure,gr20 ; return address is closure new_procedure_interrupt - LDW -3(0,31),20 ; return address offset - ADD 20,31,20 ; return address + LDW -3(0,gr31),gr20 ; return address offset + ADD gr20,gr31,gr20 ; return address new_interrupt_common ;; r20 holds address of procedure object ;; r1 = number of parameters - ADDI 1,1,1 ; add 1 for rs_continuation - COPY 1,31 ; preserve number of registers + ADDI 1,gr1,gr1 ; add 1 for rs_continuation + COPY gr1,gr31 ; preserve number of registers - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_continuation,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg1,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg2,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg3,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg4,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg5,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg6,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg7,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg8,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg9,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg10,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg11,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg12,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg13,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg14,-4(0,rs_stack) - ADDIB,<,N -1,1,save_regs_done + ADDIB,<,N -1,gr1,save_regs_done STWM rs_arg15,-4(0,rs_stack) - ;;ADDIB,<,N -1,1,save_regs_done + ;;ADDIB,<,N -1,gr1,save_regs_done ;;STWM 25,-4(0,rs_stack) - ;;ADDIB,<,N -1,1,save_regs_done + ;;ADDIB,<,N -1,gr1,save_regs_done ;;STWM 26,-4(0,rs_stack) -;; COPY 1,24 ; n pseudo homes to save -;; SUB,TR 31,24,31 ; adjust number of registers +;; COPY gr1,gr24 ; n pseudo homes to save +;; SUB,TR gr31,gr24,gr31 ; adjust number of registers save_regs_done - COPY 0,24 ; n pseudo homes to save - COPY 31,25 ; number of registers - COPY 20,26 ; entry point + COPY gr0,gr24 ; n pseudo homes to save + COPY gr31,gr25 ; number of registers + COPY gr20,gr26 ; entry point B scheme_to_interface - LDI 0x3e,28 ;comutil_new_interrupt_procedure + LDI 0x3e,gr28 ;comutil_new_interrupt_procedure ep_interface_to_scheme_new ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - LDW R'Ext_Stack_Pointer-$global$(1),rs_stack ; Setup stack pointer + LDW R'Ext_Stack_Pointer-$global$(gr1),rs_stack ; Setup stack pointer - LDWM 4(0,rs_stack),1 ; number of regs - SUBI,>= eval(ARGUMENT_REGISTERS+1),1,1 ; complement + LDWM 4(0,rs_stack),gr1 ; number of regs + SUBI,>= eval(ARGUMENT_REGISTERS+1),gr1,gr1 ; complement B,N interface_to_scheme_new_allregs - BLR 1,0 + BLR gr1,gr0 NOP interface_to_scheme_new_allregs - ;;LDWM 4(0,rs_stack),26 + ;;LDWM 4(0,rs_stack),gr26 ;;NOP - ;;LDWM 4(0,rs_stack),25 + ;;LDWM 4(0,rs_stack),gr25 ;;NOP LDWM 4(0,rs_stack),rs_arg15 NOP @@ -1715,34 +1786,34 @@ interface_to_scheme_new_allregs invoke_primitive original_invoke_primitive - DEPI 0,31,2,31 ; clear privilege bits - LDW 0(0,31),26 ; get offset + DEPI 0,31,2,gr31 ; clear privilege bits + LDW 0(0,gr31),gr26 ; get offset ADDIL L'hppa_primitive_table-$global$,rc_static_area - LDWX 26(0,31),26 ; get primitive - LDW R'hppa_primitive_table-$global$(1),25 - EXTRU 26,31,DATUM_LENGTH,24 ; get primitive index - STW 26,REGBLOCK_PRIMITIVE + LDWX indexed(gr26,(0,gr31)),gr26 ; get primitive + LDW R'hppa_primitive_table-$global$(gr1),gr25 + EXTRU gr26,31,DATUM_LENGTH,gr24 ; get primitive index + STW gr26,REGBLOCK_PRIMITIVE ADDIL L'Primitive_Arity_Table-$global$,rc_static_area - LDW R'Primitive_Arity_Table-$global$(1),17 - LDWX,S 24(0,25),25 ; find primitive entry point + LDW R'Primitive_Arity_Table-$global$(gr1),gr17 + LDWX,S indexed(gr24,(0,gr25)),gr25 ; find primitive entry point ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - STW rs_stack,R'Ext_Stack_Pointer-$global$(1) ; Update stack pointer + STW rs_stack,R'Ext_Stack_Pointer-$global$(gr1) ; Update stack pointer ADDIL L'Free-$global$,rc_static_area - LDWX,S 24(0,17),17 ; primitive arity - STW rs_free,R'Free-$global$(1) ; Update free + LDWX,S indexed(gr24,(0,gr17)),gr17 ; primitive arity + STW rs_free,R'Free-$global$(gr1) ; Update free .CALL RTNVAL=GR ; out=28 - BLE 0(4,25) ; Call primitive - COPY 31,2 ; Setup return address + BLE 0(spr4,gr25) ; Call primitive + COPY gr31,gr2 ; Setup return address ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - LDW R'Ext_Stack_Pointer-$global$(1),rs_stack ; Setup stack pointer + LDW R'Ext_Stack_Pointer-$global$(gr1),rs_stack ; Setup stack pointer COPY rc_val,rs_val ; Move result to val - SH2ADD 17,rs_stack,rs_stack ; pop frame + SH2ADD gr17,rs_stack,rs_stack ; pop frame LDWM 4(0,rs_stack),rc_arg1 ; return address as object B ep_interface_to_scheme_2 ;;DEP rs_quad,TC_START,TC_LENGTH,rc_arg2 ; return address as address - STW 0,REGBLOCK_PRIMITIVE + STW gr0,REGBLOCK_PRIMITIVE ;;; The BLE in invoke_primitive can jump here. ;;; The primitive index is in gr24 @@ -1750,14 +1821,14 @@ original_invoke_primitive cross_segment_call ADDIL L'Primitive_Procedure_Table-$global$,rc_static_area - LDW R'Primitive_Procedure_Table-$global$(1),22 - LDWX,S 24(0,22),22 + LDW R'Primitive_Procedure_Table-$global$(gr1),gr22 + LDWX,S indexed(gr24,(0,gr22)),gr22 B,N $$dyncall ; ignore the return address invoke_primitive_1_preserving STWM rs_continuation,-4(0,rs_stack) STWM rs_arg1,-4(0,rs_stack) - BB,< 31,31,invoke_primitive + BB,< gr31,31,invoke_primitive NOP BL,N do_preserve_1,gt1 NOP @@ -1767,7 +1838,7 @@ invoke_primitive_2_preserving STWM rs_continuation,-4(0,rs_stack) STWM rs_arg2,-4(0,rs_stack) STWM rs_arg1,-4(0,rs_stack) - BB,< 31,31,invoke_primitive + BB,< gr31,31,invoke_primitive NOP BL,N do_preserve_2,gt1 NOP @@ -1777,41 +1848,41 @@ new_pushing_args_invoke_primitive ;; not used because the compiled generates code to do the pushes ;; This will have to be modified to accomodate the *MAGIC* comment in ;; invoke_primitive. - DEPI 0,31,2,31 ; clear privilege bits + DEPI 0,31,2,gr31 ; clear privilege bits STWM rs_continuation,-4(0,rs_stack) - LDW 0(0,31),26 ; get offset + LDW 0(0,gr31),gr26 ; get offset ADDIL L'hppa_primitive_table-$global$,rc_static_area - LDWX 26(0,31),26 ; get primitive - LDW R'hppa_primitive_table-$global$(1),25 - EXTRU 26,31,DATUM_LENGTH,24 ; get primitive index - STW 26,REGBLOCK_PRIMITIVE ; store primitive + LDWX indexed(gr26,(0,gr31)),gr26 ; get primitive + LDW R'hppa_primitive_table-$global$(gr1),gr25 + EXTRU gr26,31,DATUM_LENGTH,gr24 ; get primitive index + STW gr26,REGBLOCK_PRIMITIVE ; store primitive ADDIL L'Primitive_Arity_Table-$global$,rc_static_area - LDW R'Primitive_Arity_Table-$global$(1),26 - LDWX,S 24(0,25),25 ; find primitive entry point - LDWX,S 24(0,26),26 ; primitive arity + LDW R'Primitive_Arity_Table-$global$(gr1),gr26 + LDWX,S indexed(gr24,(0,gr25)),gr25 ; find primitive entry point + LDWX,S indexed(gr24,(0,gr26)),gr26 ; primitive arity STWM rs_continuation,-4(0,rs_stack) BL push_arg_registers,rs_continuation - COPY 26,29 + COPY gr26,gr29 ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - STW rs_stack,R'Ext_Stack_Pointer-$global$(1) ; Update stack pointer - COPY 26,17 ; a C callee saves reg + STW rs_stack,R'Ext_Stack_Pointer-$global$(gr1) ; Update stack pointer + COPY gr26,gr17 ; a C callee saves reg ADDIL L'Free-$global$,rc_static_area - STW rs_free,R'Free-$global$(1) ; Update free + STW rs_free,R'Free-$global$(gr1) ; Update free .CALL RTNVAL=GR ; out=28 - BLE 0(4,25) ; Call primitive - COPY 31,2 ; Setup return address + BLE 0(spr4,gr25) ; Call primitive + COPY gr31,gr2 ; Setup return address ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - LDW R'Ext_Stack_Pointer-$global$(1),rs_stack ; Setup stack pointer - COPY 28,2 ; Move result to val - SH2ADD 17,rs_stack,rs_stack ; pop frame - LDWM 4(0,rs_stack),26 ; return address as object + LDW R'Ext_Stack_Pointer-$global$(gr1),rs_stack ; Setup stack pointer + COPY gr28,gr2 ; Move result to val + SH2ADD gr17,rs_stack,rs_stack ; pop frame + LDWM 4(0,rs_stack),gr26 ; return address as object STW 0,REGBLOCK_PRIMITIVE ; clear primitive B ep_interface_to_scheme_2 - DEP rs_quad,TC_START,TC_LENGTH,26 ; return address as address + DEP rs_quad,TC_START,TC_LENGTH,gr26 ; return address as address ;; vector_cons: @@ -1836,7 +1907,7 @@ vector_cons_loop LDI TC_VECTOR,gt4 ; load type code COPY gt1,rs_val - BLE 0(5,rs_continuation) ; return! + BLE 0(spr5,rs_continuation) ; return! DEP gt4,TC_START,TC_LENGTH,rs_val ; tag result ;; string_allocate: @@ -1849,17 +1920,17 @@ string_allocate ADD rs_arg1,rs_free,gt2 ; end of data (-(9+round)) ;; if no space, use primitive COMBF,< gt2,rs_memtop,invoke_primitive_1_preserving - SHD 0,rs_arg1,2,gt3 ; scale down to word - STB 0,8(0,gt2) ; end-of-string #\NUL + SHD gr0,rs_arg1,2,gt3 ; scale down to word + STB gr0,8(0,gt2) ; end-of-string #\NUL LDO 2(gt3),gt3 ; total word size (-1) STWS,MB rs_arg1,4(0,rs_free) ; store string length; free++ SH2ADD gt3,rs_free,rs_free ; allocate! DEPI TC_NMV,TC_START,TC_LENGTH,gt3 ; tag header STW gt3,0(0,gt1) ; store nmv header - LDI TC_STRING,1 + LDI TC_STRING,gr1 COPY gt1,rs_val - BLE 0(5,rs_continuation) ; return! - DEP 1,TC_START,TC_LENGTH,rs_val ; tag result + BLE 0(spr5,rs_continuation) ; return! + DEP gr1,TC_START,TC_LENGTH,rs_val ; tag result ;; floating_vector_cons: ;; continuation in rs_continuation @@ -1867,35 +1938,35 @@ string_allocate ;; returns vector in rs_val floating_vector_cons ZDEP rs_arg1,31,DATUM_LENGTH,rs_arg1 ; length as machine word - ; STW 0,0(0,rs_free) ; make heap parseable + ; STW gr0,0(0,rs_free) ; make heap parseable DEPI 4,31,3,rs_free ; bump free past header COPY rs_free,gt1 ; return value SH3ADD rs_arg1,rs_free,gt2 ; end of data (-1) ;; if no space, use primitive COMBF,< gt2,rs_memtop,invoke_primitive_1_preserving - SHD rs_arg1,0,31,gt3 ; scale, harmless in delay slot + SHD rs_arg1,gr0,31,gt3 ; scale, harmless in delay slot LDO 4(gt2),rs_free ; allocate! DEPI TC_NMV,TC_START,TC_LENGTH,gt3 ; tag header STW gt3,0(0,gt1) ; store nmv header COPY gt1,rs_val - BLE 0(5,rs_continuation) ; return! + BLE 0(spr5,rs_continuation) ; return! DEPI TC_FLONUM,TC_START,TC_LENGTH,rs_val ; tag result define(define_floating_point_util, "flonum_$1 - COPY 22,17 ; preserve regs - STW 2,REGBLOCK_VAL ; preserve val - COPY 22,17 ; preserve regs - COPY 21,16 - COPY 19,15 + COPY gr22,gr17 ; preserve regs + STW gr2,REGBLOCK_VAL ; preserve val + COPY gr22,gr17 ; preserve regs + COPY gr21,gr16 + COPY gr19,gr15 .CALL ARGW0=FR,ARGW1=FU,RTNVAL=FU ;fpin=105;fpout=104; - BL $2,2 - COPY 31,14 - COPY 15,19 - COPY 16,21 + BL $2,gr2 + COPY gr31,gr14 + COPY gr15,gr19 + COPY gr16,gr21 LDW REGBLOCK_VAL,rs_val ; restore val - COPY 17,22 - BE 0(5,14) + COPY gr17,gr22 + BE 0(spr5,gr14) LDW REGBLOCK_MEMTOP,rs_memtop") define_floating_point_util(sin,sin) @@ -1911,38 +1982,38 @@ define_floating_point_util(ceiling,ceil) define_floating_point_util(floor,floor) flonum_atan2 - COPY 22,17 ; preserve regs - STW 2,REGBLOCK_VAL ; preserve val - COPY 21,16 - COPY 19,15 + COPY gr22,gr17 ; preserve regs + STW gr2,REGBLOCK_VAL ; preserve val + COPY gr21,gr16 + COPY gr19,gr15 .CALL ARGW0=FR,ARGW1=FU,ARGW2=FR,ARGW3=FU,RTNVAL=FU ;fpin=105,107;fpout=104; - BL atan2,2 - COPY 31,14 - COPY 15,19 - COPY 16,21 + BL atan2,gr2 + COPY gr31,gr14 + COPY gr15,gr19 + COPY gr16,gr21 LDW REGBLOCK_VAL,rs_val ; restore val - COPY 17,22 - BE 0(5,14) + COPY gr17,gr22 + BE 0(spr5,gr14) LDW REGBLOCK_MEMTOP,rs_memtop compiled_code_bkpt - LDO -8(31),31 ; bump back to entry point - ;; COPY 19,25 ; Preserve Dynamic link - LDB -6(0,31),29 ; get entry frame size + LDO -8(gr31),gr31 ; bump back to entry point + ;; COPY gr19,gr25 ; Preserve Dynamic link + LDB -6(0,gr31),gr29 ; get entry frame size B bkpt_hook_to_interface - LDI 0x3c,28 + LDI 0x3c,gr28 compiled_closure_bkpt - LDO -12(31),31 ; bump back to entry point - LDB -6(0,31),29 ; frame size + LDO -12(gr31),gr31 ; bump back to entry point + LDB -6(0,gr31),gr29 ; frame size B bkpt_hook_to_interface - LDI 0x3d,28 + LDI 0x3d,gr28 closure_entry_bkpt - LDO -8(31),31 ; bump back to entry point - LDB -6(0,31),29 ; frame size + LDO -8(gr31),gr31 ; bump back to entry point + LDB -6(0,gr31),gr29 ; frame size B bkpt_hook_to_interface - LDI 0x3c,28 + LDI 0x3c,gr28 ;; On arrival, 31 has a return address. The word at the return ;; address has the offset between the return address and the @@ -1951,21 +2022,21 @@ closure_entry_bkpt ;; Used: 29, 28, 26, 25, fp11, fp10 [31] copy_closure_pattern - LDW -3(0,31),29 ; offset + LDW -3(0,gr31),gr29 ; offset DEPI 4,31,3,rs_free ; quad align - ADD 29,31,29 ; addr of pattern - LDWS,MA 4(0,29),28 ; load pattern header - LDO 8(rs_free),25 ; preserve for FDC & FIC - STWS,MA 28,4(0,rs_free) ; store pattern header - FLDDS,MA 8(0,29),10 ; load entry - FLDDS,MA 8(0,29),11 - FSTDS,MA 10,8(0,rs_free) ; store entry - FSTDS,MA 11,8(0,rs_free) - FDC 0(0,25) + ADD gr29,gr31,gr29 ; addr of pattern + LDWS,MA 4(0,gr29),gr28 ; load pattern header + LDO 8(rs_free),gr25 ; preserve for FDC & FIC + STWS,MA gr28,4(0,rs_free) ; store pattern header + FLDDS,MA 8(0,gr29),fpr10 ; load entry + FLDDS,MA 8(0,gr29),fpr11 + FSTDS,MA fpr10,8(0,rs_free) ; store entry + FSTDS,MA fpr11,8(0,rs_free) + FDC 0(0,gr25) FDC 0(0,rs_free) SYNC - FIC 0(5,25) - BE 4(5,31) + FIC 0(spr5,gr25) + BE 4(spr5,gr31) SYNC ;; On arrival, 31 has a return address and 1 contains the number of @@ -1975,29 +2046,29 @@ copy_closure_pattern ;; Used: 29, 28, 26, 25, fp11, fp10 [31, 1] copy_multiclosure_pattern - LDW -3(0,31),29 ; offset + LDW -3(0,gr31),gr29 ; offset DEPI 4,31,3,rs_free ; quad align - ADD 29,31,29 ; addr of pattern - LDWS,MA 4(0,29),28 ; load pattern header - LDO 12(rs_free),25 ; preserve for FIC - STWS,MA 28,4(0,rs_free) ; store pattern header - LDI -16,26 ; FDC index + ADD gr29,gr31,gr29 ; addr of pattern + LDWS,MA 4(0,gr29),gr28 ; load pattern header + LDO 12(rs_free),gr25 ; preserve for FIC + STWS,MA gr28,4(0,rs_free) ; store pattern header + LDI -16,gr26 ; FDC index copy_multiclosure_pattern_loop - FLDDS,MA 8(0,29),10 ; load entry - FLDDS,MA 8(0,29),11 - FSTDS,MA 10,8(0,rs_free) ; store entry - FSTDS,MA 11,8(0,rs_free) - ADDIB,> -1,1,copy_multiclosure_pattern_loop - FDC 26(0,21) - - LDWS,MA 4(0,29),28 ; load pattern tail - COPY rs_free,26 - STWS,MA 28,4(0,rs_free) ; store pattern tail - FDC 0(0,26) + FLDDS,MA 8(0,gr29),fpr10 ; load entry + FLDDS,MA 8(0,gr29),fpr11 + FSTDS,MA fpr10,8(0,rs_free) ; store entry + FSTDS,MA fpr11,8(0,rs_free) + ADDIB,> -1,gr1,copy_multiclosure_pattern_loop + FDC indexed(gr26,(0,gr21)) + + LDWS,MA 4(0,gr29),gr28 ; load pattern tail + COPY rs_free,gr26 + STWS,MA gr28,4(0,rs_free) ; store pattern tail + FDC indexed(0,(0,gr26)) SYNC - FIC 0(5,25) - BE 4(5,31) ; return + FIC indexed(0,(spr5,gr25)) + BE 4(spr5,gr31) ; return SYNC ;;; This code clobbers 2,31,gt1-gt4. @@ -2026,17 +2097,17 @@ copy_multiclosure_pattern_loop preserve_registers do_preserve_1 - ADD,TR 0,0,gt2 ; extra words + ADD,TR gr0,gr0,gt2 ; extra words do_preserve_2 LDI 1,gt2 ; extra words - LDWM 4(0,rs_stack),1 ; pop arg 1 - COMICLR,= 0,gt2,0 - LDWM 4(0,rs_stack),2 ; pop arg 2 + LDWM 4(0,rs_stack),gr1 ; pop arg 1 + COMICLR,= 0,gt2,gr0 + LDWM 4(0,rs_stack),gr2 ; pop arg 2 STW rs_stack,REGBLOCK_COMPILER_TEMP ;; CHANGE?: LDW 0(0,rs_stack),gt3 ; real return address - LDW -4(0,31),gt4 ; integer register mask + LDW -4(0,gr31),gt4 ; integer register mask ;; The following sequence preserves all the integer registers (except 0, ;; 1, and 31) if specified in the mask. Of course, certain bits set @@ -2044,210 +2115,208 @@ do_preserve_2 ;; code uses a few of them. BB,>=,N gt4,2,pskip2 - STWM 2,-4(0,rs_stack) + STWM gr2,-4(0,rs_stack) pskip2 BB,>=,N gt4,3,pskip3 - STWM 3,-4(0,rs_stack) + STWM gr3,-4(0,rs_stack) pskip3 BB,>=,N gt4,4,pskip4 - STWM 4,-4(0,rs_stack) + STWM gr4,-4(0,rs_stack) pskip4 BB,>=,N gt4,5,pskip5 - STWM 5,-4(0,rs_stack) + STWM gr5,-4(0,rs_stack) pskip5 BB,>=,N gt4,6,pskip6 - STWM 6,-4(0,rs_stack) + STWM gr6,-4(0,rs_stack) pskip6 BB,>=,N gt4,7,pskip7 - STWM 7,-4(0,rs_stack) + STWM gr7,-4(0,rs_stack) pskip7 BB,>=,N gt4,8,pskip8 - STWM 8,-4(0,rs_stack) + STWM gr8,-4(0,rs_stack) pskip8 BB,>=,N gt4,9,pskip9 - STWM 9,-4(0,rs_stack) + STWM gr9,-4(0,rs_stack) pskip9 BB,>=,N gt4,10,pskip10 - STWM 10,-4(0,rs_stack) + STWM gr10,-4(0,rs_stack) pskip10 BB,>=,N gt4,11,pskip11 - STWM 11,-4(0,rs_stack) + STWM gr11,-4(0,rs_stack) pskip11 BB,>=,N gt4,12,pskip12 - STWM 12,-4(0,rs_stack) + STWM gr12,-4(0,rs_stack) pskip12 BB,>=,N gt4,13,pskip13 - STWM 13,-4(0,rs_stack) + STWM gr13,-4(0,rs_stack) pskip13 BB,>=,N gt4,14,pskip14 - STWM 14,-4(0,rs_stack) + STWM gr14,-4(0,rs_stack) pskip14 BB,>=,N gt4,15,pskip15 - STWM 15,-4(0,rs_stack) + STWM gr15,-4(0,rs_stack) pskip15 BB,>=,N gt4,16,pskip16 - STWM 16,-4(0,rs_stack) + STWM gr16,-4(0,rs_stack) pskip16 BB,>=,N gt4,17,pskip17 - STWM 17,-4(0,rs_stack) + STWM gr17,-4(0,rs_stack) pskip17 BB,>=,N gt4,18,pskip18 - STWM 18,-4(0,rs_stack) + STWM gr18,-4(0,rs_stack) pskip18 BB,>=,N gt4,19,pskip19 - STWM 19,-4(0,rs_stack) + STWM gr19,-4(0,rs_stack) pskip19 BB,>=,N gt4,20,pskip20 - STWM 20,-4(0,rs_stack) + STWM gr20,-4(0,rs_stack) pskip20 BB,>=,N gt4,21,pskip21 - STWM 21,-4(0,rs_stack) + STWM gr21,-4(0,rs_stack) pskip21 BB,>=,N gt4,22,pskip22 - STWM 22,-4(0,rs_stack) + STWM gr22,-4(0,rs_stack) pskip22 BB,>=,N gt4,23,pskip23 - STWM 23,-4(0,rs_stack) + STWM gr23,-4(0,rs_stack) pskip23 BB,>=,N gt4,24,pskip24 - STWM 24,-4(0,rs_stack) + STWM gr24,-4(0,rs_stack) pskip24 BB,>=,N gt4,25,pskip25 - STWM 25,-4(0,rs_stack) + STWM gr25,-4(0,rs_stack) pskip25 BB,>=,N gt4,26,pskip26 - STWM 26,-4(0,rs_stack) + STWM gr26,-4(0,rs_stack) pskip26 BB,>=,N gt4,27,pskip27 - STWM 27,-4(0,rs_stack) + STWM gr27,-4(0,rs_stack) pskip27 BB,>=,N gt4,28,pskip28 - STWM 28,-4(0,rs_stack) + STWM gr28,-4(0,rs_stack) pskip28 BB,>=,N gt4,29,pskip29 - STWM 29,-4(0,rs_stack) + STWM gr29,-4(0,rs_stack) pskip29 BB,>=,N gt4,30,pskip30 - STWM 30,-4(0,rs_stack) + STWM gr30,-4(0,rs_stack) pskip30 - LDO -4(31),6 ; skip to previous word + LDO -4(gr31),gr6 ; skip to previous word BB,>=,N gt4,31,preserve_skip_object_homes - LDBS,MB -1(0,6),7 ; count of pseudo regs - LDO 64(4),8 ; address of first home + LDBS,MB -1(0,gr6),gr7 ; count of pseudo regs + LDO 64(rs_regblock),gr8 ; address of first home -pohloop LDBS,MB -1(0,6),9 ; pseudo reg number - LDO -1(7),7 - SH3ADDL 9,8,9 - LDW 0(0,9),10 ; value in home - COMB,<> 0,7,pohloop - STWM 10,-4(0,rs_stack) +pohloop LDBS,MB -1(0,gr6),gr9 ; pseudo reg number + LDO -1(gr7),gr7 + SH3ADDL gr9,gr8,gr9 + LDW 0(0,gr9),gr10 ; value in home + COMB,<> gr0,gr7,pohloop + STWM gr10,-4(0,rs_stack) preserve_skip_object_homes - DEPI 0,31,2,6 ; align to first word - COPY rs_stack,11 ; preserve sp + DEPI 0,31,2,gr6 ; align to first word + COPY rs_stack,gr11 ; preserve sp BB,>=,N gt4,0,preserve_skip_float_regs DEPI 0,31,3,rs_stack ; align float - LDWM -4(0,6),8 ; float mask + LDWM -4(0,gr6),gr8 ; float mask - BB,>=,N 8,0,pfskp0 - FSTDS,MB 0,-8(0,rs_stack) -pfskp0 BB,>=,N 8,1,pfskp1 - FSTDS,MB 1,-8(0,rs_stack) -pfskp1 BB,>=,N 8,2,pfskp2 - FSTDS,MB 2,-8(0,rs_stack) -pfskp2 BB,>=,N 8,3,pfskp3 - FSTDS,MB 3,-8(0,rs_stack) -pfskp3 BB,>=,N 8,4,pfskp4 - FSTDS,MB 4,-8(0,rs_stack) -pfskp4 BB,>=,N 8,5,pfskp5 - FSTDS,MB 5,-8(0,rs_stack) -pfskp5 BB,>=,N 8,6,pfskp6 - FSTDS,MB 6,-8(0,rs_stack) -pfskp6 BB,>=,N 8,7,pfskp7 - FSTDS,MB 7,-8(0,rs_stack) -pfskp7 BB,>=,N 8,8,pfskp8 - FSTDS,MB 8,-8(0,rs_stack) -pfskp8 BB,>=,N 8,9,pfskp9 - FSTDS,MB 9,-8(0,rs_stack) -pfskp9 BB,>=,N 8,10,pfskp10 - FSTDS,MB 10,-8(0,rs_stack) -pfskp10 BB,>=,N 8,11,pfskp11 - FSTDS,MB 11,-8(0,rs_stack) -pfskp11 BB,>=,N 8,12,pfskp12 - FSTDS,MB 12,-8(0,rs_stack) -pfskp12 BB,>=,N 8,13,pfskp13 - FSTDS,MB 13,-8(0,rs_stack) -pfskp13 BB,>=,N 8,14,pfskp14 - FSTDS,MB 14,-8(0,rs_stack) -pfskp14 BB,>=,N 8,15,pfskp15 - FSTDS,MB 15,-8(0,rs_stack) -pfskp15 BB,>=,N 8,16,pfskp16 - FSTDS,MB 16,-8(0,rs_stack) -pfskp16 BB,>=,N 8,17,pfskp17 - FSTDS,MB 17,-8(0,rs_stack) -pfskp17 BB,>=,N 8,18,pfskp18 - FSTDS,MB 18,-8(0,rs_stack) -pfskp18 BB,>=,N 8,19,pfskp19 - FSTDS,MB 19,-8(0,rs_stack) -pfskp19 BB,>=,N 8,20,pfskp20 - FSTDS,MB 20,-8(0,rs_stack) -pfskp20 BB,>=,N 8,21,pfskp21 - FSTDS,MB 21,-8(0,rs_stack) -pfskp21 BB,>=,N 8,22,pfskp22 - FSTDS,MB 22,-8(0,rs_stack) -pfskp22 BB,>=,N 8,23,pfskp23 - FSTDS,MB 23,-8(0,rs_stack) -pfskp23 BB,>=,N 8,24,pfskp24 - FSTDS,MB 24,-8(0,rs_stack) -pfskp24 BB,>=,N 8,25,pfskp25 - FSTDS,MB 25,-8(0,rs_stack) -pfskp25 BB,>=,N 8,26,pfskp26 - FSTDS,MB 26,-8(0,rs_stack) -pfskp26 BB,>=,N 8,27,pfskp27 - FSTDS,MB 27,-8(0,rs_stack) -pfskp27 BB,>=,N 8,28,pfskp28 - FSTDS,MB 28,-8(0,rs_stack) -pfskp28 BB,>=,N 8,29,pfskp29 - FSTDS,MB 29,-8(0,rs_stack) -pfskp29 BB,>=,N 8,30,pfskp30 - FSTDS,MB 30,-8(0,rs_stack) -pfskp30 BB,>=,N 8,31,pfskp31 - FSTDS,MB 31,-8(0,rs_stack) + BB,>=,N gr8,0,pfskp0 + FSTDS,MB fpr0,-8(0,rs_stack) +pfskp0 BB,>=,N gr8,1,pfskp1 + FSTDS,MB fpr1,-8(0,rs_stack) +pfskp1 BB,>=,N gr8,2,pfskp2 + FSTDS,MB fpr2,-8(0,rs_stack) +pfskp2 BB,>=,N gr8,3,pfskp3 + FSTDS,MB fpr3,-8(0,rs_stack) +pfskp3 BB,>=,N gr8,4,pfskp4 + FSTDS,MB fpr4,-8(0,rs_stack) +pfskp4 BB,>=,N gr8,5,pfskp5 + FSTDS,MB fpr5,-8(0,rs_stack) +pfskp5 BB,>=,N gr8,6,pfskp6 + FSTDS,MB fpr6,-8(0,rs_stack) +pfskp6 BB,>=,N gr8,7,pfskp7 + FSTDS,MB fpr7,-8(0,rs_stack) +pfskp7 BB,>=,N gr8,8,pfskp8 + FSTDS,MB fpr8,-8(0,rs_stack) +pfskp8 BB,>=,N gr8,9,pfskp9 + FSTDS,MB fpr9,-8(0,rs_stack) +pfskp9 BB,>=,N gr8,10,pfskp10 + FSTDS,MB fpr10,-8(0,rs_stack) +pfskp10 BB,>=,N gr8,11,pfskp11 + FSTDS,MB fpr11,-8(0,rs_stack) +pfskp11 BB,>=,N gr8,12,pfskp12 + FSTDS,MB fpr12,-8(0,rs_stack) +pfskp12 BB,>=,N gr8,13,pfskp13 + FSTDS,MB fpr13,-8(0,rs_stack) +pfskp13 BB,>=,N gr8,14,pfskp14 + FSTDS,MB fpr14,-8(0,rs_stack) +pfskp14 BB,>=,N gr8,15,pfskp15 + FSTDS,MB fpr15,-8(0,rs_stack) +pfskp15 BB,>=,N gr8,16,pfskp16 + FSTDS,MB fpr16,-8(0,rs_stack) +pfskp16 BB,>=,N gr8,17,pfskp17 + FSTDS,MB fpr17,-8(0,rs_stack) +pfskp17 BB,>=,N gr8,18,pfskp18 + FSTDS,MB fpr18,-8(0,rs_stack) +pfskp18 BB,>=,N gr8,19,pfskp19 + FSTDS,MB fpr19,-8(0,rs_stack) +pfskp19 BB,>=,N gr8,20,pfskp20 + FSTDS,MB fpr20,-8(0,rs_stack) +pfskp20 BB,>=,N gr8,21,pfskp21 + FSTDS,MB fpr21,-8(0,rs_stack) +pfskp21 BB,>=,N gr8,22,pfskp22 + FSTDS,MB fpr22,-8(0,rs_stack) +pfskp22 BB,>=,N gr8,23,pfskp23 + FSTDS,MB fpr23,-8(0,rs_stack) +pfskp23 BB,>=,N gr8,24,pfskp24 + FSTDS,MB fpr24,-8(0,rs_stack) +pfskp24 BB,>=,N gr8,25,pfskp25 + FSTDS,MB fpr25,-8(0,rs_stack) +pfskp25 BB,>=,N gr8,26,pfskp26 + FSTDS,MB fpr26,-8(0,rs_stack) +pfskp26 BB,>=,N gr8,27,pfskp27 + FSTDS,MB fpr27,-8(0,rs_stack) +pfskp27 BB,>=,N gr8,28,pfskp28 + FSTDS,MB fpr28,-8(0,rs_stack) +pfskp28 BB,>=,N gr8,29,pfskp29 + FSTDS,MB fpr29,-8(0,rs_stack) +pfskp29 BB,>=,N gr8,30,pfskp30 + FSTDS,MB fpr30,-8(0,rs_stack) +pfskp30 BB,>=,N gr8,31,pfskp31 + FSTDS,MB fpr31,-8(0,rs_stack) pfskp31 preserve_skip_float_regs BB,>=,N gt4,1,preserve_skip_float_homes - DEPI 0,31,3,22 ; align float + DEPI 0,31,3,gr22 ; align float - LDBS,MB -1(0,6),7 - LDO 64(4),8 + LDBS,MB -1(0,gr6),gr7 + LDO 64(rs_regblock),gr8 -pfhloop LDBS,MB -1(0,6),9 ; pseudo reg number - LDO -1(7),7 - FLDDX,S 9(0,8),4 ; value in home - COMB,<> 0,7,pfhloop - FSTDS,MB 4,-8(0,rs_stack) +pfhloop LDBS,MB -1(0,gr6),gr9 ; pseudo reg number + LDO -1(gr7),gr7 + FLDDX,S indexed(gr9,(0,gr8)),fpr4 ; value in home + COMB,<> gr0,gr7,pfhloop + FSTDS,MB fpr4,-8(0,rs_stack) preserve_skip_float_homes - SUB 11,22,11 ; non-marked bytes pushed - SHD 0,11,2,11 ; non-marked words pushed - DEPI TC_NMV,TC_START,TC_LENGTH,11 ; -> non-marked vector header - STWM 11,-4(0,rs_stack) ; push header or nothing - LDW REGBLOCK_COMPILER_TEMP,6 ; original stack pointer - STWM gt3,-4(0,rs_stack) ; re-push return address + SUB gr11,gr22,gr11 ; non-marked bytes pushed + SHD gr0,gr11,2,gr11 ; non-marked words pushed + DEPI TC_NMV,TC_START,TC_LENGTH,gr11 ; -> non-marked vector header + STWM gr11,-4(0,rs_stack) ; push header or nothing + LDW REGBLOCK_COMPILER_TEMP,gr6 ; original stack pointer + STWM gt3,-4(0,rs_stack) ; re-push return address DEP rs_quad,TC_START,TC_LENGTH,gt3 ; object->address - SUB gt3,31,gt3 ; offset of mask + SUB gt3,gr31,gt3 ; offset of mask STWM gt3,-4(0,rs_stack) ; push offset in stack - SUB 6,22,6 ; bytes pushed - SHD 0,6,2,6 ; words pushed - STWM 6,-4(0,rs_stack) ; push number of words on stack + SUB gr6,gr22,gr6 ; bytes pushed + SHD gr0,gr6,2,gr6 ; words pushed + STWM gr6,-4(0,rs_stack) ; push number of words on stack LDI 5,gt3 ; REFLECT_CODE_RESTORE_REGS - LDI TC_POSITIVE_FIXNUM,6 - DEP 6,TC_START,TC_LENGTH,gt3 STWM gt3,-4(0,rs_stack) ; push into stack LDW REGBLOCK_REFLECT_TO_INTERFACE,gt3 STWM gt3,-4(0,rs_stack) ; push into stack COMICLR,= 0,gt2,0 ; extra words = 0? - STWM 2,-4(0,rs_stack) ; push arg 2 + STWM gr2,-4(0,rs_stack) ; push arg 2 BV 0(gt1) - STWM 1,-4(0,rs_stack) ; push arg 1 + STWM gr1,-4(0,rs_stack) ; push arg 1 ep_interface_to_scheme_restore restore_registers ADDIL L'Ext_Stack_Pointer-$global$,rc_static_area - LDW R'Ext_Stack_Pointer-$global$(1),rs_stack ; Setup stack pointer + LDW R'Ext_Stack_Pointer-$global$(gr1),rs_stack ; Setup stack pointer LDWM 4(0,rs_stack),gt2 ; offset of mask LDWM 4(0,rs_stack),gt1 ; return address DEP rs_quad,TC_START,TC_LENGTH,gt1 ; object->address SUB gt1,gt2,gt1 ; address of mask LDW -4(0,gt1),gt4 ; mask - LDWM 4(0,rs_stack),11 ; non marked vector header + LDWM 4(0,rs_stack),gr11 ; non marked vector header - LDO -4(gt1),12 ; addr of object mask + LDO -4(gt1),gr12 ; addr of object mask BB,>=,N gt4,31,restore_float_homes - LDB -1(0,12),7 ; count of object homes -1 - LDO 5(7),7 ; normalize - SHD 0,7,2,7 ; into words - SH2ADDL 7,0,7 ; into bytes - SUB 12,7,12 ; addr past floating mask + LDB -1(0,gr12),gr7 ; count of object homes -1 + LDO 5(gr7),gr7 ; normalize + SHD gr0,gr7,2,gr7 ; into words + SH2ADDL gr7,gr0,gr7 ; into bytes + SUB gr12,gr7,gr12 ; addr past floating mask ;; NOTE: The following sequence restores all the integer registers if @@ -2257,193 +2326,193 @@ restore_registers restore_float_homes BB,>=,N gt4,1,restore_skip_float_homes - COPY 12,6 + COPY gr12,gr6 BB,>=,N gt4,0,restore_float_homes_continue - LDO -4(6),6 ; skip past floating-poing mask + LDO -4(gr6),gr6 ; skip past floating-poing mask restore_float_homes_continue - LDO -1(6),6 ; address of count - LDO 64(4),8 ; address of first home - LDBS,MA -1(0,6),7 ; count of pseudo regs - SUB 6,7,6 ; address of first number - -rfhloop LDBS,MA 1(0,6),9 ; pseudo reg number - FLDDS,MA 8(0,rs_stack),4 ; floating-point value - LDO -1(7),7 - COMB,<> 0,7,rfhloop - FSTDX 4,9(0,8) + LDO -1(gr6),gr6 ; address of count + LDO 64(rs_regblock),gr8 ; address of first home + LDBS,MA -1(0,gr6),gr7 ; count of pseudo regs + SUB gr6,gr7,gr6 ; address of first number + +rfhloop LDBS,MA 1(0,gr6),gr9 ; pseudo reg number + FLDDS,MA 8(0,rs_stack),fpr4 ; floating-point value + LDO -1(gr7),gr7 + COMB,<> gr0,gr7,rfhloop + FSTDX fpr4,indexed(gr9,(0,gr8)) restore_skip_float_homes BB,>=,N gt4,0,restore_skip_float_regs - LDW -4(0,12),8 ; floating-point mask - BB,>=,N 8,31,rfskp31 - FLDDS,MA 8(0,rs_stack),31 -rfskp31 BB,>=,N 8,30,rfskp30 - FLDDS,MA 8(0,rs_stack),30 -rfskp30 BB,>=,N 8,29,rfskp29 - FLDDS,MA 8(0,rs_stack),29 -rfskp29 BB,>=,N 8,28,rfskp28 - FLDDS,MA 8(0,rs_stack),28 -rfskp28 BB,>=,N 8,27,rfskp27 - FLDDS,MA 8(0,rs_stack),27 -rfskp27 BB,>=,N 8,26,rfskp26 - FLDDS,MA 8(0,rs_stack),26 -rfskp26 BB,>=,N 8,25,rfskp25 - FLDDS,MA 8(0,rs_stack),25 -rfskp25 BB,>=,N 8,24,rfskp24 - FLDDS,MA 8(0,rs_stack),24 -rfskp24 BB,>=,N 8,23,rfskp23 - FLDDS,MA 8(0,rs_stack),23 -rfskp23 BB,>=,N 8,22,rfskp22 - FLDDS,MA 8(0,rs_stack),22 -rfskp22 BB,>=,N 8,21,rfskp21 - FLDDS,MA 8(0,rs_stack),21 -rfskp21 BB,>=,N 8,20,rfskp20 - FLDDS,MA 8(0,rs_stack),20 -rfskp20 BB,>=,N 8,19,rfskp19 - FLDDS,MA 8(0,rs_stack),19 -rfskp19 BB,>=,N 8,18,rfskp18 - FLDDS,MA 8(0,rs_stack),18 -rfskp18 BB,>=,N 8,17,rfskp17 - FLDDS,MA 8(0,rs_stack),17 -rfskp17 BB,>=,N 8,16,rfskp16 - FLDDS,MA 8(0,rs_stack),16 -rfskp16 BB,>=,N 8,15,rfskp15 - FLDDS,MA 8(0,rs_stack),15 -rfskp15 BB,>=,N 8,14,rfskp14 - FLDDS,MA 8(0,rs_stack),14 -rfskp14 BB,>=,N 8,13,rfskp13 - FLDDS,MA 8(0,rs_stack),13 -rfskp13 BB,>=,N 8,12,rfskp12 - FLDDS,MA 8(0,rs_stack),12 -rfskp12 BB,>=,N 8,11,rfskp11 - FLDDS,MA 8(0,rs_stack),11 -rfskp11 BB,>=,N 8,10,rfskp10 - FLDDS,MA 8(0,rs_stack),10 -rfskp10 BB,>=,N 8,9,rfskp9 - FLDDS,MA 8(0,rs_stack),9 -rfskp9 BB,>=,N 8,8,rfskp8 - FLDDS,MA 8(0,rs_stack),8 -rfskp8 BB,>=,N 8,7,rfskp7 - FLDDS,MA 8(0,rs_stack),7 -rfskp7 BB,>=,N 8,6,rfskp6 - FLDDS,MA 8(0,rs_stack),6 -rfskp6 BB,>=,N 8,5,rfskp5 - FLDDS,MA 8(0,rs_stack),5 -rfskp5 BB,>=,N 8,4,rfskp4 - FLDDS,MA 8(0,rs_stack),4 -rfskp4 BB,>=,N 8,3,rfskp3 - FLDDS,MA 8(0,rs_stack),3 -rfskp3 BB,>=,N 8,2,rfskp2 - FLDDS,MA 8(0,rs_stack),2 -rfskp2 BB,>=,N 8,1,rfskp1 - FLDDS,MA 8(0,rs_stack),1 -rfskp1 BB,>=,N 8,0,rfskp0 - FLDDS,MA 8(0,rs_stack),0 + LDW -4(0,gr12),gr8 ; floating-point mask + BB,>=,N gr8,31,rfskp31 + FLDDS,MA 8(0,rs_stack),fpr31 +rfskp31 BB,>=,N gr8,30,rfskp30 + FLDDS,MA 8(0,rs_stack),fpr30 +rfskp30 BB,>=,N gr8,29,rfskp29 + FLDDS,MA 8(0,rs_stack),fpr29 +rfskp29 BB,>=,N gr8,28,rfskp28 + FLDDS,MA 8(0,rs_stack),fpr28 +rfskp28 BB,>=,N gr8,27,rfskp27 + FLDDS,MA 8(0,rs_stack),fpr27 +rfskp27 BB,>=,N gr8,26,rfskp26 + FLDDS,MA 8(0,rs_stack),fpr26 +rfskp26 BB,>=,N gr8,25,rfskp25 + FLDDS,MA 8(0,rs_stack),fpr25 +rfskp25 BB,>=,N gr8,24,rfskp24 + FLDDS,MA 8(0,rs_stack),fpr24 +rfskp24 BB,>=,N gr8,23,rfskp23 + FLDDS,MA 8(0,rs_stack),fpr23 +rfskp23 BB,>=,N gr8,22,rfskp22 + FLDDS,MA 8(0,rs_stack),fpr22 +rfskp22 BB,>=,N gr8,21,rfskp21 + FLDDS,MA 8(0,rs_stack),fpr21 +rfskp21 BB,>=,N gr8,20,rfskp20 + FLDDS,MA 8(0,rs_stack),fpr20 +rfskp20 BB,>=,N gr8,19,rfskp19 + FLDDS,MA 8(0,rs_stack),fpr19 +rfskp19 BB,>=,N gr8,18,rfskp18 + FLDDS,MA 8(0,rs_stack),fpr18 +rfskp18 BB,>=,N gr8,17,rfskp17 + FLDDS,MA 8(0,rs_stack),fpr17 +rfskp17 BB,>=,N gr8,16,rfskp16 + FLDDS,MA 8(0,rs_stack),fpr16 +rfskp16 BB,>=,N gr8,15,rfskp15 + FLDDS,MA 8(0,rs_stack),fpr15 +rfskp15 BB,>=,N gr8,14,rfskp14 + FLDDS,MA 8(0,rs_stack),fpr14 +rfskp14 BB,>=,N gr8,13,rfskp13 + FLDDS,MA 8(0,rs_stack),fpr13 +rfskp13 BB,>=,N gr8,12,rfskp12 + FLDDS,MA 8(0,rs_stack),fpr12 +rfskp12 BB,>=,N gr8,11,rfskp11 + FLDDS,MA 8(0,rs_stack),fpr11 +rfskp11 BB,>=,N gr8,10,rfskp10 + FLDDS,MA 8(0,rs_stack),fpr10 +rfskp10 BB,>=,N gr8,9,rfskp9 + FLDDS,MA 8(0,rs_stack),fpr9 +rfskp9 BB,>=,N gr8,8,rfskp8 + FLDDS,MA 8(0,rs_stack),fpr8 +rfskp8 BB,>=,N gr8,7,rfskp7 + FLDDS,MA 8(0,rs_stack),fpr7 +rfskp7 BB,>=,N gr8,6,rfskp6 + FLDDS,MA 8(0,rs_stack),fpr6 +rfskp6 BB,>=,N gr8,5,rfskp5 + FLDDS,MA 8(0,rs_stack),fpr5 +rfskp5 BB,>=,N gr8,4,rfskp4 + FLDDS,MA 8(0,rs_stack),fpr4 +rfskp4 BB,>=,N gr8,3,rfskp3 + FLDDS,MA 8(0,rs_stack),fpr3 +rfskp3 BB,>=,N gr8,2,rfskp2 + FLDDS,MA 8(0,rs_stack),fpr2 +rfskp2 BB,>=,N gr8,1,rfskp1 + FLDDS,MA 8(0,rs_stack),fpr1 +rfskp1 BB,>=,N gr8,0,rfskp0 + FLDDS,MA 8(0,rs_stack),fpr0 rfskp0 restore_skip_float_regs - BB,>=,N 11,31,rspop ; was there padding? - LDO 4(22),22 ; pop padding + BB,>=,N gr11,31,rspop ; was there padding? + LDO 4(gr22),gr22 ; pop padding rspop BB,>=,N gt4,31,restore_skip_object_homes - LDO -5(gt1),6 ; address of count - LDO 64(4),8 ; address of first home - LDBS,MA -1(0,6),7 ; count of pseudo regs - SUB 6,7,6 ; address of first number - -rohloop LDBS,MA 1(0,6),9 ; pseudo reg number - LDWM 4(0,rs_stack),10 ; value - LDO -1(7),7 - SH3ADDL 9,8,9 - COMB,<> 0,7,rohloop - STW 10,0(0,9) + LDO -5(gt1),gr6 ; address of count + LDO 64(rs_regblock),gr8 ; address of first home + LDBS,MA -1(0,gr6),gr7 ; count of pseudo regs + SUB gr6,gr7,gr6 ; address of first number + +rohloop LDBS,MA 1(0,gr6),gr9 ; pseudo reg number + LDWM 4(0,rs_stack),gr10 ; value + LDO -1(gr7),gr7 + SH3ADDL gr9,gr8,gr9 + COMB,<> gr0,gr7,rohloop + STW gr10,0(0,gr9) restore_skip_object_homes BB,>=,N gt4,30,rskip30 - LDWM 4(0,rs_stack),30 + LDWM 4(0,rs_stack),gr30 rskip30 BB,>=,N gt4,29,rskip29 - LDWM 4(0,rs_stack),29 + LDWM 4(0,rs_stack),gr29 rskip29 BB,>=,N gt4,28,rskip28 - LDWM 4(0,rs_stack),28 + LDWM 4(0,rs_stack),gr28 rskip28 BB,>=,N gt4,27,rskip27 - LDWM 4(0,rs_stack),27 + LDWM 4(0,rs_stack),gr27 rskip27 BB,>=,N gt4,26,rskip26 - LDWM 4(0,rs_stack),26 + LDWM 4(0,rs_stack),gr26 rskip26 BB,>=,N gt4,25,rskip25 - LDWM 4(0,rs_stack),25 + LDWM 4(0,rs_stack),gr25 rskip25 BB,>=,N gt4,24,rskip24 - LDWM 4(0,rs_stack),24 + LDWM 4(0,rs_stack),gr24 rskip24 BB,>=,N gt4,23,rskip23 - LDWM 4(0,rs_stack),23 + LDWM 4(0,rs_stack),gr23 rskip23 BB,>=,N gt4,22,rskip22 - LDWM 4(0,rs_stack),22 + LDWM 4(0,rs_stack),gr22 rskip22 BB,>=,N gt4,21,rskip21 - LDWM 4(0,rs_stack),21 + LDWM 4(0,rs_stack),gr21 rskip21 BB,>=,N gt4,20,rskip20 - LDWM 4(0,rs_stack),20 + LDWM 4(0,rs_stack),gr20 rskip20 BB,>=,N gt4,19,rskip19 - LDWM 4(0,rs_stack),19 + LDWM 4(0,rs_stack),gr19 rskip19 BB,>=,N gt4,18,rskip18 - LDWM 4(0,rs_stack),18 + LDWM 4(0,rs_stack),gr18 rskip18 BB,>=,N gt4,17,rskip17 - LDWM 4(0,rs_stack),17 + LDWM 4(0,rs_stack),gr17 rskip17 BB,>=,N gt4,16,rskip16 - LDWM 4(0,rs_stack),16 + LDWM 4(0,rs_stack),gr16 rskip16 BB,>=,N gt4,15,rskip15 - LDWM 4(0,rs_stack),15 + LDWM 4(0,rs_stack),gr15 rskip15 BB,>=,N gt4,14,rskip14 - LDWM 4(0,rs_stack),14 + LDWM 4(0,rs_stack),gr14 rskip14 BB,>=,N gt4,13,rskip13 - LDWM 4(0,rs_stack),13 + LDWM 4(0,rs_stack),gr13 rskip13 BB,>=,N gt4,12,rskip12 - LDWM 4(0,rs_stack),12 + LDWM 4(0,rs_stack),gr12 rskip12 BB,>=,N gt4,11,rskip11 - LDWM 4(0,rs_stack),11 + LDWM 4(0,rs_stack),gr11 rskip11 BB,>=,N gt4,10,rskip10 - LDWM 4(0,rs_stack),10 + LDWM 4(0,rs_stack),gr10 rskip10 BB,>=,N gt4,9,rskip9 - LDWM 4(0,rs_stack),9 + LDWM 4(0,rs_stack),gr9 rskip9 BB,>=,N gt4,8,rskip8 - LDWM 4(0,rs_stack),8 + LDWM 4(0,rs_stack),gr8 rskip8 BB,>=,N gt4,7,rskip7 - LDWM 4(0,rs_stack),7 + LDWM 4(0,rs_stack),gr7 rskip7 BB,>=,N gt4,6,rskip6 - LDWM 4(0,rs_stack),6 + LDWM 4(0,rs_stack),gr6 rskip6 BB,>=,N gt4,5,rskip5 - LDWM 4(0,rs_stack),5 + LDWM 4(0,rs_stack),gr5 rskip5 BB,>=,N gt4,4,rskip4 - LDWM 4(0,rs_stack),4 + LDWM 4(0,rs_stack),gr4 rskip4 BB,>=,N gt4,3,rskip3 - LDWM 4(0,rs_stack),3 + LDWM 4(0,rs_stack),gr3 rskip3 BB,>=,N gt4,2,rskip2 - LDWM 4(0,rs_stack),2 + LDWM 4(0,rs_stack),gr2 rskip2 - LDWM 4(0,rs_stack),26 ; return address - LDW REGBLOCK_VAL,2 ; interpreter val -> val reg + LDWM 4(0,rs_stack),gr26 ; return address + LDW REGBLOCK_VAL,gr2 ; interpreter val -> val reg B ep_interface_to_scheme_2 - DEP rs_quad,TC_START,TC_LENGTH,26 ; object->address + DEP rs_quad,TC_START,TC_LENGTH,gr26 ; object->address ;; Arguments in g26, g25, [and g24] (standard C argument registers) ;; utility code in g28 ;; return address for scheme_to_interface_ble (and register mask) in g31 interpreter_call - BB,< 31,31,scheme_to_interface_ble + BB,< gr31,31,scheme_to_interface_ble NOP - STWM 25,-8(0,rs_stack) ; preserve gt2 - LDO 4(31),26 ; bump past format word - LDI TC_CCENTRY,23 - DEP 23,TC_START,TC_LENGTH,26 ; set tag - STW 26,4(0,rs_stack) ; return address (gt1) + STWM gr25,-8(0,rs_stack) ; preserve gt2 + LDO 4(gr31),gr26 ; bump past format word + LDI TC_CCENTRY,gr23 + DEP gr23,TC_START,TC_LENGTH,gr26 ; set tag + STW gr26,4(0,rs_stack) ; return address (gt1) BL do_preserve_1,gt1 - COPY 28,23 ; preserve code - LDWM 4(0,rs_stack),25 - LDWM 4(0,rs_stack),26 ; reflect_to_interface - DEP rs_quad,TC_START,TC_LENGTH,26 ; untag + COPY gr28,gr23 ; preserve code + LDWM 4(0,rs_stack),gr25 + LDWM 4(0,rs_stack),gr26 ; reflect_to_interface + DEP rs_quad,TC_START,TC_LENGTH,gr26 ; untag B scheme_to_interface - COPY 23,28 ; restore code + COPY gr23,gr28 ; restore code ;; This label is used by the trap handler @@ -2454,26 +2523,26 @@ ep_scheme_hooks_high ;;; It returns from C_to_interface. ep_interface_to_C - COPY 29,28 ; Setup C value - LDW -eval(C_FRAME_SIZE+20)(0,rc_stack),2 ; Restore return address - LDW -52(0,rc_stack),18 ; Restore saved regs - LDW -56(0,rc_stack),17 - LDW -60(0,rc_stack),16 - LDW -64(0,rc_stack),15 - LDW -68(0,rc_stack),14 - LDW -72(0,rc_stack),13 - LDW -76(0,rc_stack),12 - LDW -80(0,rc_stack),11 - LDW -84(0,rc_stack),10 - LDW -88(0,rc_stack),9 - LDW -92(0,rc_stack),8 - LDW -96(0,rc_stack),7 - LDW -100(0,rc_stack),6 - LDW -104(0,rc_stack),5 - LDW -108(0,rc_stack),4 - BV 0(2) ; Return + COPY gr29,gr28 ; Setup C value + LDW -eval(C_FRAME_SIZE+20)(0,rc_stack),gr2 ; Restore return address + LDW -52(0,rc_stack),gr18 ; Restore saved regs + LDW -56(0,rc_stack),gr17 + LDW -60(0,rc_stack),gr16 + LDW -64(0,rc_stack),gr15 + LDW -68(0,rc_stack),gr14 + LDW -72(0,rc_stack),gr13 + LDW -76(0,rc_stack),gr12 + LDW -80(0,rc_stack),gr11 + LDW -84(0,rc_stack),gr10 + LDW -88(0,rc_stack),gr9 + LDW -92(0,rc_stack),gr8 + LDW -96(0,rc_stack),gr7 + LDW -100(0,rc_stack),gr6 + LDW -104(0,rc_stack),gr5 + LDW -108(0,rc_stack),gr4 + BV 0(gr2) ; Return .EXIT - LDWM -eval(C_FRAME_SIZE)(0,rc_stack),3 ; Restore last reg, pop frame + LDWM -eval(C_FRAME_SIZE)(0,rc_stack),gr3 ; Restore last reg, pop frame .PROCEND ;in=26;out=28; ;;;; Procedure to initialize this interface. @@ -2486,24 +2555,24 @@ interface_initialize .PROC .CALLINFO CALLER,FRAME=4,SAVE_RP .ENTRY - STW 2,-20(0,rc_stack) ; Preserve return address + STW gr2,-20(0,rc_stack) ; Preserve return address LDO 64(rc_stack),rc_stack ; Allocate stack frame - STW 3,-64(rc_stack) ; Preserve gr3 - FSTWS 0,-4(rc_stack) - LDW -4(rc_stack),22 - LDI 30,21 ; enable V, Z, O, U traps - OR 21,22,22 - STW 22,-4(rc_stack) - FLDWS -4(rc_stack),0 + STW gr3,-64(rc_stack) ; Preserve gr3 + FSTWS fpr0,-4(rc_stack) + LDW -4(rc_stack),gr22 + LDI 30,gr21 ; enable V, Z, O, U traps + OR gr21,gr22,gr22 + STW gr22,-4(rc_stack) + FLDWS -4(rc_stack),fpr0 ; Prepare entry points - BL known_pc,3 ; get pc + BL known_pc,gr3 ; get pc NOP known_pc -define(store_entry_point,"ADDIL L'ep_$1-known_pc,3 - LDO R'ep_$1-known_pc(1),29 - ADDIL L'$1-$global$,27 - STW 29,R'$1-$global$(1)") +define(store_entry_point,"ADDIL L'ep_$1-known_pc,gr3 + LDO R'ep_$1-known_pc(gr1),gr29 + ADDIL L'$1-$global$,gr27 + STW gr29,R'$1-$global$(gr1)") store_entry_point(interface_to_scheme_restore) store_entry_point(interface_to_scheme_new) @@ -2511,12 +2580,12 @@ define(store_entry_point,"ADDIL L'ep_$1-known_pc,3 store_entry_point(interface_to_C) changequote([,]) -define(builtin,[ADDIL L'$1-known_pc,3 - LDO R'$1-known_pc(1),26 - ADDIL L'$1_string-$global$,27 +define(builtin,[ADDIL L'$1-known_pc,gr3 + LDO R'$1-known_pc(gr1),gr26 + ADDIL L'$1_string-$global$,gr27 .CALL ARGW0=GR - BL declare_builtin,2 - LDO R'$1_string-$global$(1),25 divert(1) + BL declare_builtin,gr2 + LDO R'$1_string-$global$(gr1),gr25 divert(1) $1_string .ALIGN 8 .STRINGZ "$1" divert(0)]) @@ -2586,9 +2655,9 @@ $1_string builtin(ep_scheme_hooks_high) changequote(",") ; Return - LDW -84(rc_stack),2 ; Restore return address - LDW -64(rc_stack),3 ; Restore gr3 - BV 0(2) + LDW -84(rc_stack),gr2 ; Restore return address + LDW -64(rc_stack),gr3 ; Restore gr3 + BV 0(gr2) .EXIT LDO -64(rc_stack),rc_stack ; De-allocate stack frame .PROCEND @@ -2620,28 +2689,28 @@ cache_flush_region .PROC .CALLINFO CALLER,FRAME=0 .ENTRY - LDO 3(25),25 ; add 3 to round up - SHD 0,25,2,25 ; divide count (in longs) by 4 - COPY 25,28 ; save for FIC loop - COPY 26,29 ; save for FIC loop - LDI 16,1 ; increment - BB,>=,N 24,30,process_i_cache ; if D_CACHE is not set, + LDO 3(gr25),gr25 ; add 3 to round up + SHD gr0,gr25,2,gr25 ; divide count (in longs) by 4 + COPY gr25,gr28 ; save for FIC loop + COPY gr26,gr29 ; save for FIC loop + LDI 16,gr1 ; increment + BB,>=,N gr24,30,process_i_cache ; if D_CACHE is not set, ; skip d-cache ;;; flush_cache_fdc_loop - ADDIB,>= -1,25,flush_cache_fdc_loop - FDC,M 1(0,26) + ADDIB,>= -1,gr25,flush_cache_fdc_loop + FDC,M indexed(gr1,(0,gr26)) SYNC ;;; process_i_cache - BB,>=,N 24,31,L$exit2 ; if I_CACHE is not set, return + BB,>=,N gr24,31,L$exit2 ; if I_CACHE is not set, return ;;; flush_cache_fic_loop - ADDIB,>= -1,28,flush_cache_fic_loop - FIC,M 1(5,29) + ADDIB,>= -1,gr28,flush_cache_fic_loop + FIC,M indexed(gr1,(spr5,gr29)) ;;; L$exit2 - BV 0(2) + BV 0(gr2) .EXIT SYNC .PROCEND ;in=25,26; @@ -2670,116 +2739,116 @@ cache_flush_all .ENTRY do_d_cache - BB,>=,N 26,30,do_i_cache ; if D_CACHE is not set, + BB,>=,N gr26,30,do_i_cache ; if D_CACHE is not set, ; skip d-cache - LDW 32(0,25),31 ; 31 <- address (init. base) - LDW 44(0,25),29 ; 29 <- loop - LDW 36(0,25),23 ; 23 <- stride - LDW 40(0,25),19 ; 19 <- count + LDW 32(0,gr25),gr31 ; 31 <- address (init. base) + LDW 44(0,gr25),gr29 ; 29 <- loop + LDW 36(0,gr25),gr23 ; 23 <- stride + LDW 40(0,gr25),gr19 ; 19 <- count - LDO -1(19),19 ; decrement count - COMIB,>,N 0,19,d_sync ; if (count < 0), no flush - COMIB,=,N 1,29,d_direct_l - COMIB,=,N 2,29,d_assoc2_l - COMIB,=,N 4,29,d_assoc4_l + LDO -1(gr19),gr19 ; decrement count + COMIB,>,N 0,gr19,d_sync ; if (count < 0), no flush + COMIB,=,N 1,gr29,d_direct_l + COMIB,=,N 2,gr29,d_assoc2_l + COMIB,=,N 4,gr29,d_assoc4_l d_assoc_l ; set-associative flush-loop - COPY 29,20 ; 20 (lcount) <- loop + COPY gr29,gr20 ; 20 (lcount) <- loop d_set_l ; set flush-loop - LDO -1(20),20 ; decrement lcount - COMIB,<=,N 0,20,d_set_l ; if (lcount >= 0), set loop - FDCE 0(0,31) ; flush entry at (address) + LDO -1(gr20),gr20 ; decrement lcount + COMIB,<=,N 0,gr20,d_set_l ; if (lcount >= 0), set loop + FDCE 0(0,gr31) ; flush entry at (address) - LDO -1(19),19 ; decrement count - COMIB,<= 0,19,d_assoc_l ; if (count >= 0), loop - ADD 31,23,31 ; address++ + LDO -1(gr19),gr19 ; decrement count + COMIB,<= 0,gr19,d_assoc_l ; if (count >= 0), loop + ADD gr31,gr23,gr31 ; address++ B do_i_cache ; next SYNC ; synchronize after flush d_assoc4_l ; 4-way set-associative loop - FDCE 0(0,31) ; flush entry at (*address) - FDCE 0(0,31) ; flush entry at (*address) - FDCE 0(0,31) ; flush entry at (*address) - FDCE,M 23(0,31) ; flush entry at (*address++) - COMIB,< 0,19,d_assoc4_l ; if (count > 0), loop - LDO -1(19),19 ; decrement count + FDCE indexed(0,(0,gr31)) ; flush entry at (*address) + FDCE indexed(0,(0,gr31)) ; flush entry at (*address) + FDCE indexed(0,(0,gr31)) ; flush entry at (*address) + FDCE,M indexed(gr23,(0,gr31)) ; flush entry at (*address++) + COMIB,< 0,gr19,d_assoc4_l ; if (count > 0), loop + LDO -1(gr19),gr19 ; decrement count B do_i_cache ; next SYNC ; synchronize after flush d_assoc2_l ; 2-way set-associative loop - FDCE 0(0,31) ; flush entry at (*address) - FDCE,M 23(0,31) ; flush entry at (*address++) - COMIB,< 0,19,d_assoc2_l ; if (count > 0), loop - LDO -1(19),19 ; decrement count + FDCE indexed(0,(0,gr31)) ; flush entry at (*address) + FDCE,M indexed(gr23,(0,gr31)) ; flush entry at (*address++) + COMIB,< 0,gr19,d_assoc2_l ; if (count > 0), loop + LDO -1(gr19),gr19 ; decrement count B do_i_cache ; next SYNC ; synchronize after flush d_direct_l ; direct-mapped flush loop - FDCE,M 23(0,31) ; flush entry at (*address++) - COMIB,< 0,19,d_direct_l ; if (count > 0), loop - LDO -1(19),19 ; decrement count + FDCE,M indexed(gr23,(0,gr31)) ; flush entry at (*address++) + COMIB,< 0,gr19,d_direct_l ; if (count > 0), loop + LDO -1(gr19),gr19 ; decrement count d_sync SYNC ; synchronize after flush do_i_cache - BB,>=,N 26,31,L$exit1 ; if I_CACHE is not set, return + BB,>=,N gr26,31,L$exit1 ; if I_CACHE is not set, return - LDW 8(0,25),31 ; 31 <- address (init. base) - LDW 20(0,25),29 ; 29 <- loop - LDW 12(0,25),23 ; 23 <- stride - LDW 16(0,25),19 ; 19 <- count + LDW 8(0,gr25),gr31 ; 31 <- address (init. base) + LDW 20(0,gr25),gr29 ; 29 <- loop + LDW 12(0,gr25),gr23 ; 23 <- stride + LDW 16(0,gr25),gr19 ; 19 <- count - LDO -1(19),19 ; decrement count - COMIB,>,N 0,19,i_sync ; if (count < 0), no flush - COMIB,=,N 1,29,i_direct_l - COMIB,=,N 2,29,i_assoc2_l - COMIB,=,N 4,29,i_assoc4_l + LDO -1(gr19),gr19 ; decrement count + COMIB,>,N 0,gr19,i_sync ; if (count < 0), no flush + COMIB,=,N 1,gr29,i_direct_l + COMIB,=,N 2,gr29,i_assoc2_l + COMIB,=,N 4,gr29,i_assoc4_l i_assoc_l ; set-associative flush-loop - COPY 29,20 ; 20 (lcount) <- loop + COPY gr29,gr20 ; 20 (lcount) <- loop i_set_l ; set flush-loop - LDO -1(20),20 ; decrement lcount - COMIB,<=,N 0,20,i_set_l ; if (lcount >= 0), set loop - FICE 0(5,31) ; flush entry at (address) + LDO -1(gr20),gr20 ; decrement lcount + COMIB,<=,N 0,gr20,i_set_l ; if (lcount >= 0), set loop + FICE 0(spr5,gr31) ; flush entry at (address) - LDO -1(19),19 ; decrement count - COMIB,<= 0,19,i_assoc_l ; if (count >= 0), loop - ADD 31,23,31 ; address++ + LDO -1(gr19),gr19 ; decrement count + COMIB,<= 0,gr19,i_assoc_l ; if (count >= 0), loop + ADD gr31,gr23,gr31 ; address++ B i_skips ; next SYNC ; synchronize after flush i_assoc4_l ; 4-way set-associative loop - FICE 0(5,31) ; flush entry at (*address) - FICE 0(5,31) ; flush entry at (*address) - FICE 0(5,31) ; flush entry at (*address) - FICE,M 23(5,31) ; flush entry at (*address++) - COMIB,< 0,19,i_assoc4_l ; if (count > 0), loop - LDO -1(19),19 ; decrement count + FICE indexed(0,(spr5,gr31)) ; flush entry at (*address) + FICE indexed(0,(spr5,gr31)) ; flush entry at (*address)) + FICE indexed(0,(spr5,gr31)) ; flush entry at (*address) + FICE,M indexed(gr23,(spr5,gr31)) ; flush entry at (*address++) + COMIB,< 0,gr19,i_assoc4_l ; if (count > 0), loop + LDO -1(gr19),gr19 ; decrement count B i_skips ; next SYNC ; synchronize after flush i_assoc2_l ; 2-way set-associative loop - FICE 0(5,31) ; flush entry at (*address) - FICE,M 23(5,31) ; flush entry at (*address++) - COMIB,< 0,19,i_assoc2_l ; if (count > 0), loop - LDO -1(19),19 ; decrement count + FICE indexed(0,(spr5,gr31)) ; flush entry at (*address) + FICE,M indexed(gr23,(spr5,gr31)) ; flush entry at (*address++) + COMIB,< 0,gr19,i_assoc2_l ; if (count > 0), loop + LDO -1(gr19),gr19 ; decrement count B i_skips ; next SYNC ; synchronize after flush i_direct_l ; direct-mapped flush loop - FICE,M 23(5,31) ; flush entry at (*address++) - COMIB,< 0,19,i_direct_l ; if (count > 0), loop - LDO -1(19),19 ; decrement count + FICE,M indexed(gr23,(spr5,gr31)) ; flush entry at (*address++) + COMIB,< 0,gr19,i_direct_l ; if (count > 0), loop + LDO -1(gr19),gr19 ; decrement count i_sync SYNC ; synchronize after flush @@ -2792,39 +2861,39 @@ i_skips NOP L$exit1 - BV 0(2) + BV 0(gr2) .EXIT NOP .PROCEND ;in=25,26; bkpt_normal_proceed - BL bkpt_normal_cont,1 ; Get PC - DEP 0,31,2,1 + BL bkpt_normal_cont,gr1 ; Get PC + DEPI 0,31,2,gr1 bkpt_normal_cont - LDW bkpt_normal_ep-bkpt_normal_cont(0,1),1 ; entry point - BV 0(1) ; Invoke + LDW bkpt_normal_ep-bkpt_normal_cont(0,gr1),gr1 ; entry point + BV 0(gr1) ; Invoke NOP ; Slot for first instruction bkpt_normal_ep NOP ; Slot for fall through bkpt_plus_proceed - COMB,= 1,1,bkpt_plus_t ; Slot for first instruction + COMB,= gr1,gr1,bkpt_plus_t ; Slot for first instruction NOP ; Slot for second instruction - STWM 1,-4(0,rs_stack) ; Preserve 1 - BL bkpt_plus_cont_f,1 ; Get PC - DEP 0,31,2,1 + STWM gr1,-4(0,rs_stack) ; Preserve 1 + BL bkpt_plus_cont_f,gr1 ; Get PC + DEPI 0,31,2,gr1 bkpt_plus_cont_f - LDW bkpt_plus_ep-bkpt_plus_cont_f(0,1),1 ; entry point - BV 0(1) ; Invoke - LDWM 4(0,rs_stack),1 + LDW bkpt_plus_ep-bkpt_plus_cont_f(0,gr1),gr1 ; entry point + BV 0(gr1) ; Invoke + LDWM 4(0,rs_stack),gr1 bkpt_plus_t - STWM 1,-4(0,rs_stack) ; Preserve 1 - BL bkpt_plus_cont_t,1 ; Get PC - DEP 0,31,2,1 + STWM gr1,-4(0,rs_stack) ; Preserve 1 + BL bkpt_plus_cont_t,gr1 ; Get PC + DEPI 0,31,2,gr1 bkpt_plus_cont_t - LDW bkpt_plus_bt-bkpt_plus_cont_t(0,1),1 ; entry point - BV 0(1) ; Invoke - LDWM 4(0,rs_stack),1 + LDW bkpt_plus_bt-bkpt_plus_cont_t(0,gr1),gr1 ; entry point + BV 0(gr1) ; Invoke + LDWM 4(0,rs_stack),gr1 bkpt_plus_ep NOP ; Slot for fall through bkpt_plus_bt @@ -2832,36 +2901,36 @@ bkpt_plus_bt bkpt_minus_proceed_start bkpt_minus_t - STWM 1,-4(0,rs_stack) ; Preserve 1 - BL bkpt_minus_cont_t,1 ; Get PC - DEP 0,31,2,1 + STWM gr1,-4(0,rs_stack) ; Preserve 1 + BL bkpt_minus_cont_t,gr1 ; Get PC + DEPI 0,31,2,gr1 bkpt_minus_cont_t - LDW bkpt_minus_bt-bkpt_minus_cont_t(0,1),1 ; entry point - BV 0(1) ; Invoke - LDWM 4(0,rs_stack),1 + LDW bkpt_minus_bt-bkpt_minus_cont_t(0,gr1),gr1 ; entry point + BV 0(gr1) ; Invoke + LDWM 4(0,rs_stack),gr1 bkpt_minus_proceed - COMB,= 1,1,bkpt_minus_t ; Slot for first instruction + COMB,= gr1,gr1,bkpt_minus_t ; Slot for first instruction NOP ; Slot for second instruction - STWM 1,-4(0,rs_stack) ; Preserve 1 - BL bkpt_minus_cont_f,1 ; Get PC - DEP 0,31,2,1 + STWM gr1,-4(0,rs_stack) ; Preserve 1 + BL bkpt_minus_cont_f,gr1 ; Get PC + DEPI 0,31,2,gr1 bkpt_minus_cont_f - LDW bkpt_minus_ep-bkpt_minus_cont_f(0,1),1 ; entry point - BV 0(1) ; Invoke - LDWM 4(0,rs_stack),1 + LDW bkpt_minus_ep-bkpt_minus_cont_f(0,gr1),gr1 ; entry point + BV 0(gr1) ; Invoke + LDWM 4(0,rs_stack),gr1 bkpt_minus_ep NOP ; Slot for fall through bkpt_minus_bt NOP ; Slot for branch target bkpt_closure_proceed - BL bkpt_closure_cont,1 - DEP 0,31,2,1 + BL bkpt_closure_cont,gr1 + DEPI 0,31,2,gr1 bkpt_closure_cont - LDW bkpt_closure_entry-bkpt_closure_cont(0,1),25 - LDW bkpt_closure_closure-bkpt_closure_cont(0,1),31 - BV 0(25) - COPY 31,25 + LDW bkpt_closure_entry-bkpt_closure_cont(0,gr1),gr25 + LDW bkpt_closure_closure-bkpt_closure_cont(0,gr1),gr31 + BV 0(gr25) + COPY gr31,gr25 bkpt_closure_closure NOP ; Closure object pointer bkpt_closure_entry -- 2.25.1